1. To perform process simulation use different process corner model files: SS (Slow PMOS Slow NMOS), FF (Fast PMOS Fast NMOS), SF (Slow PMOS Fast NMOS) and FS (Fast PMOS Slow NMOS) for parameter under consideration.
2. For temperature and voltage variations perform parametric analysis. Vary temperature say from -60 to 100 degree Celsius in 10 steps. Similarly analysis can be done for voltage variations.
3. You can also make manual corners (say C1) for more rigorous analysis by using combinations of different process, temperature and voltage corners (e.g. C1: SS, 100 C and 1.75 V in 180 nm node) and observe behavior of parameter under consideration for newly made corner (C1).
A few things to ponder about in case you are planning for accuracy of the results.
1. Do you want to have lowest abstraction at gate level or transistor level. Skew corner (SF,ST) process models will have to be aliased accordingly.
2. Are you going to use extracted parasitics ( layout extracted parasitics will themselve change RC annotations based on process and temperature.) So for extracted parasitics you may have to decouple temperature and process sweeps as seperate runs.