Hi,
I am working with a platform to deal with signals based on FPGA boards.
I have currently built the reference design on GitHub ( https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2), and the Linux software core with it.
I now need to reduce the voltage of the signal output on DAC, but I have no idea where I can start to modify the project. I am wondering if someone has solved similar problems before and can give me a hint what I can do.
Thank you!
Basically modern fpga's operate at low power and higher current loads.
mp and soc can use in the design to reduce the output voltage.
Verilog programming can help us to some extent.
I suggest you visit the constraint file: https://github.com/analogdevicesinc/hdl/blob/master/projects/daq2/kcu105/system_constr.xdc
Then, you may have to reduce the reference voltage that is used with the DAQ with a statement like:
set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks location]
Good luck.
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