I am trying to implement a processor tile on FPGA using vivado but it is taking too long to synthesize design due to large amount of Instruction and Data Memory.
Currently, I have put complete machine code of a simple GCD code in the instruction memory and generated the bit stream file.
But I cannot afford to wait for hours everytime I try to synthesize processor for a new code.
There must be a way to interact with internal memory of FPGA so I can put machine code in the memory and connect to instruction memory of processor.
In this way I will generate bit stream file of processor tile only once. Burn it to FPGA and put different machine code every time to test a different code.
I have gone through documentation of board and explored many other documents but could not find something useful at my level.
Board I'm using: Nexys A7-100T.
Software: Vivado 2019.2
Look at these papers that may be useful :
https://www.nxp.com/docs/en/application-note/AN2889.pdf
https://s3.cern.ch/inspire-prod-files-2/2c5d61959702bc2b4cd6bb342488a735
Article Hardware Considerations for Tensor Implementation and Analys...
https://www.sciencedirect.com/topics/computer-science/field-programmable-gate-arrays
https://www.sciencedirect.com/topics/earth-and-planetary-sciences/field-programmable-gate-array
Article An inter-FPGA communication bus with error detection and dyn...
- Badges
- Science topic
- Similar topics
- Biological Science
- Bioecology
- Systems Ecology
- Landscape Ecology
- Connectivity