I am designing a new SRAM cell .I want to check its suitability at low voltage as compare to conventional SRAM cell. What should I do?
Practical Low power design using G Yeap (chapter -6)
Since it is SRAM , delay seems to be an important consideration.
As you intend to address low voltages, there are a few things that you'll need to check:
- Noise margin
- Power consumption (both static and dynamic)
- Data retention (also including variations on the power supply)
- Speed or delay - If you care about it
In contrast to what Aparna said, SRAM does not necessarily imply a need for high speed. In some applications speed doesn't matter, but static power consumption does. Here, SRAM has a clear benefit over DRAM as it doesn't need refreshing.
Noise margin is the most severe and frequently overlooked problem in low-voltage SRAM. Low noise margin also contribute to data retention problems. The simplest way to test noise margin in design is to either connect to internal nodes in simulation workbench transient noise generators, or use Cadence transient noise simulator with large noise multiplier (~10-30) factor.
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