How to design port in cst ?

Ff Ff @Ff-Ff-64

05 November 2022 0 4K Report

I am having multiple layers

one layer output in substrate 1 is connected with vias in substrate 2

I want to see output on the vias in substrate 2

But its showing errors as memory exhausted or mesh issues

I don't know if my approach is right also as I am not able to calculate k value while design port.

Can anyone help me out with this

Thanks!

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