The type-3 PLL can maintain the estimation performance during frequency ramp while the conventional SRF-PLL has the inability in tracking frequency ramp with zero steady-state errors. The key characteristic of the type-3 PLL may make it become a promising candidate applied in grid-connected converters. However, the gain margin (GM) of the type-3 PLL is related to the phase margin (PM), and the GM is negative, which may cause instability problem in some applications. Therefore, how to deal with the negative gain margin issue of the type-3 PLL?
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