How to make a fair utilized area comparison between three designs; one of them uses 4-input LUT, the second one uses 6-input LUT, and the last one which is an Altera based uses ALUTs ( Adaptive LUT). Can I calculate the equivalent gate size/number for each case?
LUTs and flip-flops are the basic resources of the FPGA, but they are always packed together
into slices containing some of each. Depending on what you do with the LUT or flip-flop you may not
be able to use the other resource of the slice. Usually, the slice count is a good first-order indication
for fit because it represents the number of slices the design would use if no non-related logic
is packed into the same slice. The FPGA can generally hold more logic than this, but when
you exceed this point and start to pack unrelated logic into the same slice, it becomes harder
to meet timing constraints. You don't need the board to test out the capacity of your device,
just a copy of ISE tools. If you build a simple project that contains the number of IP cores
you want and has at least a few inputs and outputs to prevent the cores from being optimized
away, you can see whether it will fit or not and if it does, what sort of timing you might expect.
This article compares in the last section two results with same FPGA families with different type Virtex-4QV and virtex5:
- Badges
- Science topic
- Similar topics
- Engineering
- Computer Engineering