Hello everyone. I'm designing a 5-level diode-clamped inverter and I have met the following issue: as time passes (0 to 0.5 second simulation) I find a crossover distortion in the output sine wave (filtered) that can be mitigated by increasing the DC capacitors (those which divide the Vdc input into Vdc/2).
To prove this, I have simulated the inverter replacing these capacitors with ideal DC sources (Vdc/2 rated each one) and the crossover distortion dissapears.
As far as I understand, this means that I should have large capacitors in my real circuit, the question is: how to calculate them analytically?
Just as in any load regulated source, use impedance ratio of source to load and choose 1% or better ratio. This includes reactive and ESR values of the capacitor.
The ideal Voltage source has 0 impedance.
EE since 1975
Hi Mauricio,
Could you please post some details, such as block diagrams or waveforms ?
-Sanjay
Hello Marc and Sanjoy. I've found out the origin of my problem: deficient energy recovery path for the "lower capacitors". It produced a gradual discharge and unbalance in the voltage levels. That's why the system worked when I tested it with DC sources: they don't discharge.
I solved the problem revising the diagrams. All working well now.
My advice: Don't trust much those "multilevel inverter topologies with reduced swiches", they hide several drawbacks.
Thank you for your cooperation!
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