Half Adder=2 logic dates ,one EX-OR  gate plus one AND gate

Full adder Two Haf adder plus one OR gate

Dear Professor

Ex-OR gate required 2 AND gate, 2 NOT gate and 1 OR gate interns of AOI logic gate only. So for full adder 6 AND gate, 3 OR gate and 4 NOT gate, this is equal to which i mention.

If only AOI gates then half adder 6(3A,1 O,2 l )and 13 for full

http://www.dsm.fordham.edu/~moniot/Classes/CompOrganization/binary-adder/node5.html

Thanks Aparna Murthy and Priyadarsini Mishra for your contribution

Sorry it is 12 for full adder

For carry c =xy +yz+zx

4 gates , 3A and one O

For sum S   = x'y'z + xy'z' + x'yz' + xyz

3 I, 4A , 1 O = 8

So total 8 + 4 = 12

For OR gate number of input various

In sum Boolean equation is used as 4 input OR gate. In general, comparative purpose Fan in will consider as same

It depend how you use the technology. If you design at transistor level (full custom), you can design a CMOS adder with 20 transistors and a full Arithmetic and logical unit with 32 transistors (excluding the fast carry propagation)

It is based on the technology.

https://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/20-arithmetic/10-adders/halfadd-fulladd.html

http://www.electronicshub.org/half-adder-and-full-adder-circuits/

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