For ultra-high-speed analog to digital converters in latest CMOS technology how does power vary in sampling speed and/or effective number of bits?
The answer may be a formula or a trend (e.g. linear or quadratic in sampling rate, exponential in the number of bits, or something like this). It is also possible to have different answers for different types of ADCs, but I preferably need to know it for the best type ADC available for tens of Gsamp/sec in 7nm CMOS and for the highest number of bits available
For a given topology, power scales about linearly with sampling rate. This is due to the fact that static power consumption can be considered constant (often negligible) while dynamic power scales with the number of transistors switching (scaling with the frequency). The influence of the analog input circuitry is more or less negligible.
This said, different technologies are easily compared by comparing the number of transistors required (and eventually differences in the average switching frequency of individual signal paths). The nominal (not necessary "effective") number of bits clearly has an influence on the number of transistors, the scaling factor eventually differing between topologies. (Buf - just an educated guess - not more than linearly.)
A short google search found currently available single ADCs of 5.4 GSPS @ 12 Bits (e2v), 3 GSPS @ 14 Bits (Analog, TI)). Analog states "28 nm technology" for this converter, the others will not differ significantly. You may use the information available from these manufacturers to assess power consumption dependencies more in detail.
Hope this helps
dear Moshe,
I think that the starting point for this discussion is the typical FOM used for ADC performance comparison:
FOM=Power/(Sampling Rate* 2^ENOB)
Based on that, power is assumed to scale linearly with the sampling rate and exponentially with ENOB (in properly designed ADC, ENOB should not be too different from the actual number of output bits to avoid unessential power overhead). Increasing ENOB requires analog design effort (matching, bias currents, larger capacitor values...) to keep all errors below quantization and this justifies an exponential impact on power (even if the HW architectural complexity scales just linearly with the number of output bits).
Having said that, in order to have a better insight on the trend in advanced technologies, I suggest you to have a look to Boris Murmann's survey, which is available online and provides a lot of information about ADC papers published in top international conferences, which can be useful to analyze the trends for different ADCs, different technologies, etc...:
http://web.stanford.edu/~murmann/adcsurvey.html
Power consumption actually is dependant on technology, ADC architecture number of bits and sampling frequency. Formulas can be derived for typical ADC architectures but from experience working with state-of-the-art ADC, the best is to compare the performance of existing products, then scaling to a smaller lithography for future products is also feasible if your point is to estimate the power consumption of future products.
However if you intend to use ADC IP from the latest 7 nm technology available from IC founders, it is unlikely that those will be state of the art in terms of sampling frequency/resolution. Some companies have developed ultra-high performance IP that could be mapped onto a specific technology but this is not straightforward... particularly if you intend to integrate them with e.g. digital logic in a SoC.
For standalone products in the range of converters you are considering (large number of bits and tens of GSps), you could check Analog IQ, Teledyne e2v and Fujitsu who offer the current state of the art ADC products, for which performance data are available, though not realized in the "to be available soon" 7nm process.
It is likely that in the near future photonic ADC will be available, you will find relevant papers about their performance in the literature (no commercial product available yet as far as I am aware).
I could also recommend the following book;
High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications - Springer 2018 - ISBN : 3319620118
Regards