Leakage in FinFETs depend on several physical parameters of the transistor itself. However, it mainly has to do with the electrostatic control of the channel.

In the case of a planar MOSFET, leakage mainly happens far from the channel, usually > 5 nm below the surface, since the gate cannot control the leakage paths that are away from it.

Now, in the case of FinFETs, you basically have a thin body which is fully depleted and has no doping variation throughout the body, hence reducing the body effect (Vt variation due to substrate bias). Also, you have this very thin body being controlled by a gate from more that one side, reducing the leakage paths far from the gate and increasing the overall control of the gate over the entire body of the transistor. However, please note that in order to have lower leakage in a FinFET, there are several parameters that have to be taken into account, for example, the shape of the Fin (triangular Fins control the leakage better), the gate length to Fin ratio (leakage is better suppressed if the Fin thickness is equal or < than Lg), among others. Which provide lower DIBL, reduced short channel effects and even lower SS. This is why it has been previously said by Dr. Chenming Hu, inventor of FinFETs, that the new scaling parameter of transistors is the body thickness.

If you want to understand better how a FinFET controls the leakage, you can imagine a simpler version (what we now call ultra thin body FETs), which are normally built on fully depleted ultra thin body SOI wafers. In this case as in FinFETs, the gate can control the channel over the entire thickness of the body, hence providing similar electrostatic control over the transistor.