.

The full text of the design challenge can be found

in the attached file. Please notice carefully these

bounding conditions: (a) the solution will be in the

form of a simple all-analog (continuous-time and

continuous-amplitude) circuit; (b) you have to use

LTSPICE, and [only] its CMOS models to realize it;

(c) you have but a single 1V supply to power it all;

(d) you are invited to maximize the output swing,

(which is implied to be a voltage Vo that need not

be loaded -- which in certain sense renders it as

useless in practice, although a rail-to-rail buffer

might be added to address this matter).

.

Notice that there is no requirement for the output

to be sinusoidal (as shown in their single figure);

but any circuit that produces a near-binary output

is regarded as too simple a challenge for expert

circuit designers.

.

The Lone Arranger

I have to admit that I currently have absolutely no idea how to achieve such a transfer function. The good thing: I'm not qualified as a participant :)

.

Neither am I. Nor, I suspect, are

most of the people who've been

participating in these threads.

.

But, in a sense, that is why it has

been raised here. Are we any less

competent that the young people?

.

The Lone Arranger

Let's see whether Cyril or Josef will chime in.

Not to be forgotten: Lutz and Glen are sources

of wisdom and knowledge as well.

.

Good suggestion. I have alerted them

to this new head-scratcher in the earlier

romp, which is running out of novelty.

.

The Lone Arranger

.

It must be very tricky circuit :-)

But Josef do not work with SPICE, mostly with pen and paper only :-)

Good luck for all

Josef

At night I thought a little :-)

Several comparators and switchis and differential amplifier of course.

Josef

It would be better done in the current domain... one transconductor, current sources, switches and several current mirrors with different gain can do the job... plus one i-to-v converter... all in cmos of course.... i cannot go through details now...

@ all

The funny (or 'tricky') thing is to only use these 4 MOSFET(pair)s !

I'm not sure whether the solution would be a sea of MOSFETs, constituting some comparators an opamps.

BTW: if somebody comes up with a circuit: I've got LTSpice up and running. So I could run some simulation(s) unless it is excessive work.

@ Josef

Thanks for a first inspiration to follow.

Joseph, I use my imagination as a SPICE:)

Dreher, I think with "the funny (or 'tricky') thing to only use these 4 MOSFET(pair)s" you are very close to the solution:)

Now here is my funny "fully analog CMOS story":)

Yesterday, during the laboratory exercise on Digiatl circuits devoted to MOS and CMOS logic gates, I used a lot of effort to explain to students why the two threshold voltages VT of the NMOS and PMOS transistors in the CMOS pair should (slightly) overlap. You know the answer - since, if they not, there will be a high-impedance state when both transistors are off... and the output voltage will be undefined...

Today, thinking about how to defend the honor of the "old war horse" after the Barrie Gilbert's challenge:), I remembered my yesterday's lab exercise... and the solution emerged in my mind... Here is my "tricky" idea...

In the "conventional" CMOS pair, the two voltage thresholds are equal. So, when the input voltage crosses the middle of the supply voltage range (the input threshold of the CMOS pair), the two transistors are semi-open. The current through them (and this is the current consumed from the power supply) changes - it increases, reaches the maximum... and then decreases... like a sine "bell"... If we connect a resistor in series to the CMOS pair (and to the power supply), acting as a current-to-voltage converter, the voltage across the resistor will change in the same "sine bell" way...

If we change the proportion between both VT (VTP/VTN), keeping their sum constant, we can move the "sine bell" where we want. So, if we fabricate four CMOS pairs with linearly distributed increasing input thresholds... and connect them in parallel to the power supply (after the current-sensing resistor)... and their inputs - to the input voltage source VIN, the voltage variations across the resistor (the output voltage VOUT) will resemble the shape on the SSCS figure...

The higher the overlap of the two transistor's thresholds in the pair, the greater the maximum supply current, respectively the maximum voltage drop VOUT, will be...

If I demonstrate this circuit to my students, I would connect a LED in series to the resistor to visualize in a more attractive way the circuit operation...

In summary, my suggestion is to connect in parallel CMOS pairs with different thresholds, drive their inputs with а common VIN, and take the common output current (converted to voltage VOUT) as an output.

My Bulgarian is non-existent, but with the help of translate.google.com the document should be interpretable :)

From the description this task seems to be solvable for students. (sad: Although I studied E/E, I cannot recall to ever have fiddled with the thresholds for some CMOS logic gate.)

Let's see whether I find the time to put this thing into LTSpice.

Dreher, I think the figures inside the text are quite eloquent... and you do not need to learn Bulgarian:) But if you want, I will help you:)

It remains unclear the question of how to make VOUT bipolar (according to the SSCS figure)... Maybe we should split the power supply and insert the current-sensing resistor between its two parts? But where to take the ground from? Maybe from the lower resistor end? Or to split the resistor and take the ground from its middle point? I just throw random thoughts...

.

Fellow Friends of the Electron:

.

You are all on the right track.

"The Answer" is within reach.

.

Josef and Cyril:

.

It's very hard to understand the

behaviour of any analog circuit

of significance without the use

of (realistic & accurate) models

and simulation. However, this

much can be said: A pencil and

paper is (almost) indispensable

in thinking through a succession

of suitable topologies. Likewise

simulation is indispensable when

it comes time to accurately see

what needs to be done to make

the "idea topology" into a "real

circuit" that will do the required

thing over all variations that will

beset it in "real life".

.

This is undoubtedly the largest

difference between an academic

description of a circuit (with, of

course, a liberal dose of maths)

and real-world product design.

.

The Lone Arranger

Sorry for my really bad handwriting... in the first figure, M1 is small (W/L>1) , so that VGS is close to the threshold VTH.. and M5 is in saturation... M4 is the weak side of a mirror, of course... The i_D vs. v characteristics should resemble the one in the bottom of the first page... Similar blocks, if put together properly with different V_SW, should do the job at the requested supply.. At least I think so... my 2 c.

.

Paolo:

.

Pretty good. Now do it all with

just one current generator for

the "tail bias" -- and it must be

shown as a complete circuit

element using the one, single

supply of 1V which must also

be true of the string to make

the "offset voltages".

.

The Lone Arranger

.

Paolo and Barrie,

Would you explain to the uninitiated in this handicraft what the idea of this mess of transistors is:)? I mean a functional and intuitive explanation, which the ordinary human being can understand...

dear Cyril:

sorry for the lack of explanation. The idea is to implement an i(v,V_SW) transcaracteristics as the one in the bottom of the page: i=0 for v=V_SW (it could be called a linear trans-diode). The requested piecewise linear characteristic in the current domain, can be written as the sum of several of i(v,V_SWn) terms, for different V_SWn (possibly with a minus sign in front of them. This resembles the way poles and zeros contributions add up in a mangnitude Bode plot (but in our case the x-axis is voltage, not log of frequency and the y-axis is current, and not dB). If one can implement i(v,V_SW) , the sum can be done at a node using current mirrors with appopriate gains and polarities... and current to voltage conversion is not a problem.

Now the point is to implement the i(v,V_SW) function and this is what is done by the main block. If you have a MOS transistor (M1 in the sketch) whose gate voltage is v, the source voltage is fixed at V_SW-V_TH (V_TH: threshold voltage) by a constant voltage source and the drain is biased by a constant voltage source so that to operate it in deep triode (linear) region....

Thanks Paolo,

I think I have figured out your idea...

I am just not quite sure why the M1's drain voltage should be fixed close to its source voltage (what is the benefit of working in the triode region here)...

Dear Cyril:

M1 should be in deep triode just to have a linear rather than a quadratic increase of the drain current with v when on...

.

Fellow Wigglers:

.

The basic topology for generating

±360 degrees of high-quality sine-

wiggling is shown in the attached

PPT file. The second slide shows

the output of ±1V, when rendered

in differential form; the third slide

shows the (Gaussian) currents in

the collectors; the last slide shows

that the function is stable, in both

the input scaling magnitude and in

the output amplitude.

.

This would look very similar when

rendered in sub-threshold CMOS;

but of course the scaling (in both

axes) will be different. Note there

are some obvious problems with

the existing scaling, anyway.

.

To leave something for you to get

your brain’s clock-rate up, this will

enough for now. First, identify the

problems why even this BJT form

needs some changes in scaling to

fit into a single 1V supply.

.

The accuracy of these sine-wave

functions is excellent, and almost

perfect, as proved in the Appendix

of my JSSC paper (attached again).

.

The Lone Arranger

Dear Barrie Gilbert,

Your last comment had the effect of a nuclear bomb - dead silence after the explosion:)

But I have survived:) perhaps because, during the same early 80's, I invented a series of LED indicators based on the same current steering idea - a diode element connected in parallel to another diode element with a higher threshold voltage, diverts its current.

I see the same idea in the long-tailed (emitter-coupled) pair where the outputs of two emitter followers connected in parallel serve as "diode elements with controlled voltage thresholds". The input voltages change their thresholds and, as a result, the common emitter current is steered between the "diodes".

In your sine wiggler (the attached conceptual picture), you have further developed this idea by "nesting", like in a Russian matryoshka doll:), a few differential pairs: the innermost Q3,Q4, the middle Q2,Q5 and the outer Q1,Q6. Their outputs are alternatively inversed by simply swapping them.

Initially, only the innermost pair (Q3,Q4) is active... and the whole emitter current is divided between its transistors. When the input differential voltage increases, the middle pair (Q2,Q5) gradually connects in parallel to the innermost one... and deprives (steals:) its collector currents. Then, when the input differential voltage increases even more, the outer pair (Q1,Q6) connects in parallel to the inner pairs... and deprives the collector currents of the middle pair. Thus differential pairs are "stacked" on top of each other... and only the latter is active...

what about Taylor series of Sin??

@ Cyril

It's only a "puzzle" because you cut-away some significant parts of the circuit. Plus: most connections berween lines are not discernible as such.

Beyond that: a pattern of shorting rows and columns. I'm not completely sure about the full function, but basically it is about "controlling an N x M LED array be (N -1) + (M - 1) transistors".

If only my Bulgarian ... (But you already know that :) )

.

Cyril:

.

Given enough transistors, and enough

supply voltages. and enough freedom

in the objectives, an immensely large

number of functions are possible in electronics. That much is obvious.

.

However, the SSCS challenge is both

specific and tough: it demands that we

generate a tight solution to fit a unique definition. In particular, winning circuits

must use only 180um CMOS and must

fit within a single 1V supply. The output

quasi-sine must be in voltage form, and

having an amplitude

as large as possible within this supply

limitation. It immediately follows that

current-mode outputs aren't allowed.

.

Surely, these particulars are precisely

what makes it a worthy challenge in

circuit design.

.

So, it shouldn't be surprising that I have

spent hardly any time looking over your

LED twinkler; but enough to understand

that it bears zero relevance to the SSCS problem. I hope that others sharing this

particular thread will apply a maximum

of wisdom to devising a solution which

amply meets the design challenge, and

that they won't be distracted by further

such digressions.

.

Look at the immense amount of 'advice'

that was poured out on the 'problem' (?)

of choosing optimal feedback resistors around a simple, common-as-mud op

amp. That should surely never happen

in the annals of ResearchGate.

.

Let me add a few more pointers to the

kind of solution that will most likely be

found in the winning submission. While

not part of the original challenge, it will

be useful if the scaling amplitudes -- in

both the "x & y" dimensions (that is, the

angle input and the sine output) -- are

precise and PVT-robust. This requires

that both axes are temperature- and

supply-stable. How is this to be done,

if the VGS voltages of the transistors

(some in sub-threshold) are known to

be temperature dependent?

.

This leads to the next question, which

is: Where does the reference for these

scaling properties come from? We are

given just a 1V supply; so presumably

the needed scaling reference will most

efficiently be derived from that voltage.

This is probably no place to develop a

fancy bandgap reference (even if this

were trivial).

.

The SSCS challenge was devised to put

our best electronics instincts to the test.

Please, stay focused!

.

The Lone Arranger

Dear Barrie Gilbert,

Written by me above is not about the SSCS CMOS challenge; it is dedicated entirely to your BJT implementation in the early 80's as described in the patent US4475169:

https://www.google.com/patents/US4475169

My only purpose was to see the basic idea in this topology... this insight that gave it grounds to be recognized as an invention... I know very well that an electronic circuit can be recognized as an invention only if there is some original (not obvious constructive or technological) idea...

.

Cyril:

.

You ask:

.

> So, is there any relevance between

> these topologies? I think it is obvious...

.

Well... they are both electronic circuits,

and all electronic circuits share certain

things in common... I guess that much

is "obvious". Still, keep playing around

with the SSCS challenge and see what

you come up with... after all, there are

perhaps only some N! topologies using

N transistors! Otherwise, how would it

be possible to design thousands of op

amps all claiming special distinctions?

.

(At an ISSCC years ago I presented 32 distinctively different and specialised

analog topologies, using just two BJT transistors. That provides some basis

to suggest the N! figure; but, in reality

that number is probably far too high).

.

Here is the point. I shared that bipolar

implementation for several reasons. It

is 100% focussed on the challenge, as

issued by the esteemed branch of IEEE

called the Solid State Circuits Society;

second, it's already been implemented

in a practical IC product, and is known

to be PVT-clean; third, the SSCS invites

young inventors to realize the wiggling

function in 0.18-um CMOS; fourth, my

BJT "hint" was sufficiently incomplete

as to leave challenging questions - not

least of which is the matter of getting

the complete circuit to work with just

a single 1-V supply.

.

I could have shown the CMOS version, complete, and fully conforming to the

wording of that SSCS challenge. But, I

didn't want to spoil the fun that comes

from thinking through a tantyzing and

unusual design assignment. Anyway,

I don't think any of us wants to "try for

the prize" or is even qualified to accept

it. In view of all these considerations it

would be quite inappropriate to offer a

complete solution, before the contest

is closed. In fact, I think I have already

shown more than is wise.

.

But a "completion" challenge remains.

And how might the exact axes scaling,

raised in my previous comments, be

achieved without the use of an explicit

voltage-reference circuit? It can - only

by "cheating" a little bit, in assuming

that most modern systems will make

a 1-V supply by down-regulation of a

higher already-regulated supply voltage.

Anyway, there is no expectation that the

"X & Y" axes will be well-calibrated, let

alone, temperature-stable.

.

The Lone Arranger

.

Cyril:

.

Okay.

.

Barrie

Cyril - a great analogue producer - great laboratories - great knowledge.

Big things in circuits are taking place today in laboratories of large producers.

Barrie

what is your Idea?

could you please explain more about application and philosophy of sin wiggler?

@ Emad Ebrahimi

See the initial post (on the very top) - plus the pages linked. It's about some contest

.

Emad Ebrahimi :

.

This thread concerns a contest being

run by the Solid-State Circuits Society

of the IEEE. It is a challenge to devise

a very tricky circuit, that can accept a

low-frequency (maybe only a few Hz)

voltage input and generate a function

which they show as two full cycles of

a sinusoidal waveform, although they

also state it need not be that specific

function. The whole thing is to run on

a single 1V supply, and use only sub-

micron (180nm) CMOS. They specify

that the output (voltage) must be "as

large as possible" and require one to

use LTSpice as the simulation tool.

.

The value of this specified challenge,

to visitors to RG, is that it requires an

unusual amount of inventive thought

far beyond the sort of routine design

that is usually offered in universities.

.

Barrie

Hello guys,

I have moved my last comments to a more relevant new question:

https://www.researchgate.net/post/Can_we_think_of_the_long-tailed_pair_as_of_two_diodes_in_parallel

Please delete what you have written in your comments related to them... or move it to the new question.

Thanks,

Cyril