We are working with Sentaurus TCAD to simulate the electrical characteristics of the MOS devices. In case nano-particle embedded MOS system for memory cell application the C-V loops are experimentally measured by accumulation (A) to inversion (I) and I to A. The area of the loop indicate the performance on charge storing capacity of the devices. But in case of TCAD simulation we are unable to simulate the C-V loop. So, How to simulate C-V hysteresis loop for MOS capacitor with TCAD?
As far as I know, that is not possible. But if someone knows the trick, I'm also interested how to do it.
You would need to perform a transient simulation that includes the mechanisms of conduction through the oxide and subsequent trapping in the NPs. A lot of physics to build in as well as the numerical challenges...
I came late but as the question is basic my answer as follows:
In order to observe the C-V hysteresis of the MOS capacitor you need to subject your capacitor to an up scanning voltage ramp with relatively high speed and followed by down scanning ramp with the same speed. All what do you need to calculate is C= i/(dV/dt) where i is the current in the capacitor and dV/dt is the rate of the voltage ramp.
If you keep dV/dt constant during the scam you can display i as an indicator for C.
For controlling the hysteresis you need only to change the speed of the voltage ramp.
Best wishes
- Badges
- Science topic
- Similar topics
- Solid State Physics
- Devices