To minimize leakage through the gate dielectric one has to pattern either the gate electrode or the semiconductor or do both (the best solution). You have high gate leakage because you deposit your semiconductor everywhere on your Si/SiO2 wafer. Once you apply gate voltage you accumulate charges everywhere in the pentacene film and what you actually measure is the leakage current through your whole wafer. You can significantly reduce the leakage by scratching (patterning) pentacene film around your source and drain electrodes. This should take your leakage down to tens of nA. You can get an idea what is the minimum leakage current you can get if you measure the leakage through your dielectric without the pentacene on your gate electrode/dielectric/source electrode capacitor structure. 

Dear Leszek,

yes i did that, before depositing pentacene , i check the current flowing through  gate(80 nm, 50 um X 5000um) for V= 0 to -40, i found it doesnot exceed 0.9 nA, but as i put the pentacene on the whole wafer, leakage increases by 3 orders.

Thank you. If i still have some worries after trying this method, i shall get back to you.

First, make sure the dielectric is well made.

How did you deposite your pentacene? If spin coated, there might be peripheral leakage since liquid could go to the edge of the wafer. As Leszek said, use your probe tip and stratch on your substrate to "isolate" the pentacene of your interested device. If you used SAM layer for adhesion promotion or better charge injection, you should scratch really hard.

If the device is on a small chip. You can also try to use a sandpaper to "polish" the edge of the chip.

@Yiheng, i deposited the pentacene (Vacuum evaporation), how to check if dielectric is well made, like doing IV and CV characterization across the dielectric.

you can make a metal(your bottom gate)-insulator-metal structure by depositing a layer of metal (not patterned) on top of your wafer. Then you can measure IV. if there is a defect in the insulator, the leakage would be larger and breakdown would happen at lower voltage. Thermally grown SiO2 normally has quality, but just to make sure.

@ Yiheng , i did that usually leakge doesnot go beyond 1nA @ 40 V for 150 nm thick oxide, but when i put pentacene without patterning (i make sure that pentacene is not deposited at the edges) the leakage goes to 1u A

well, based on my experience, the leakage of 1nA is still high, you can find the pentacene TFT (bottom gate bottom contact) I made before the leakage was ~0.01nA.

Also, you can check if the leakage is dependent on the device size, say if the leakage is larger in bigger devices. (this may be an indication of the patterning issue. based on my knowledge, patterning will help to reduce leakage)

Another reason could be relating to the measurement setup. Make sure the electrical measurement setup can measure small current properly. Some times, the scanning rate of voltage will affect the current. (I found keithley 4200 had this issue)

Article Organic Thin-Film Transistors with Anodized Gate Dielectric ...

the solution is clipping each devise, I mean isolate with a  needle each transistor.

I do this with an N type polymer and exactly with the same structure (Back gate back contact)