Dear Researchers,
Hope you are safe from Coronavirus.
How can we avoid the race condition in digital circuit design? and
How can we simulate or verify if there is a race condition in the digital circuits?
Regards,
The "race" may be a problem in some of the sequential circuits/applications or some of the dynamic logic gates. It can also be problem in combinational circuits, causing undesired glitches (short-time bit errors). The examples can be increased.
Therefore, it may be difficult to write a useful answer unless you mention some details about your specific case.
"Race" is, for sure, related with some data input(s) or clock signal rising/falling later/earlier than the other (hence, the term "race").
Depending on the specific circuit, the problem may have a different nature and consequences.
It can be simulated by creating some artificial delay between the signals which are in a "race", but this may not enough to spot, understand or characterize the problem.
I cannot help further, since I don't know details of your specific case.
Best regards...
Dear Dr. Ali Zeki ,
Ramadan Karim.
Thank you for the valued information.
Best Regards,
In general, dynamic simulation is not necessarily the correct tool.
I would suggest that STA (Static Timing Analysis) and potentially CDC (Clock Domain Crossing).
These are both formal methods for analyzing the circuit.
Hope this helps,
Steven
Dear Ramzi Jaber please have a look at the following potentially useful articles:
How can we simulate or verify the race condition in the digital circuits?
https://sites.cs.ucsb.edu/~sherwood/pubs/IEEEMicro-16-race.pdf
and
Race condition in digital circuits
https://vlsiuniverse.blogspot.com/2013/08/race-condition.html
The 'race" is caused by physical delay scattered all over a logic circuit.
The "race" in combinational logic circuits is called hazard.
There is an old publication attempting to model the delays in logic circuits.
I have not followed the issue, so I do not know about any newer works.
Here you should be aware that installation of additional delay elements to control the "race" adds to computation time.
Some type of hazards in combinational logic circuits can be "masked" out form appearing at the circuit output by appropriate configuration of the gates (the logic hazard).
Regards, Maciej
Dear Dr. Maciej Rudziecki
Thank you for your answer.
I will read the attached paper.
Regards,
Here is 2-valued case, so you might need to extrapolate for 3-valued situation
regards,
Maciej R.