For a modern FinFET, hot electrons are an integral part of the operation conditions. There is really no way to prevent generation of hot electrons since they are always present in normal operation.  The important thing is to understand the overall physics of the device and have a good idea of how the cycle of hot carrier generation behaves to limit undesirable effects. 

Whenever a drain bias is applied to a MOSFET the carriers are accelerated by the out-of-equilibrium fields in the channel.  As a result, the distribution function progressively shifts to higher energy and momentum.  Hot electron is a vague term indicating the presence of this excess energy which can be equated to an equivalent temperature increase of the electron gas.  Your question asks for ways to prevent generation of hot electrons and if this is your goal, the only way is to keep the electrons as close as possible to equilibrium.  The first possibility is to reduce the electric field as hinted by the answer given by Sanat Kumar Mishra above.  This is why you were given the suggestions to use a long channel (if you keep the same bias, a longer channel lowers the field) or to lower the bias (if you keep the same channel length a lower bias lowers the field).  There is also another way to reduce the hot electrons, which is to transfer as much energy as possible to the channel by scattering.  Most of the inelastic energy transfer occurs by intervalley scattering or optical phonon emission, and just a little by acoustic phonon emission.  However, in modern devices like FinFETs, the shorter the channel the less the scattering and the transport tends to approach a quasi-ballistic regime, with very little scattering in the channel.  You would need a very long channel or very bad material to increase scattering, which is not what you want.

The problem with hot electrons in a nanoscale FinFET is not necessarily gate oxide degradation as you state, however.  First of all, in a short channel the carriers may not gain sufficient energy to create damage.  In older generation MOSFETs at medium voltages, such damage was associated to hot electrons impacting the silicon-oxide interface where they could knock out hydrogen atoms placed there to passivate the dangling bonds.  If this is a problem, deuterium can be substituted for hydrogen, because deuterium resonates differently with the interface structure and it quickly dissipates excess energy received from the hot electrons hitting the interface.  This is unlikely a problem with short FinFETS because the energies do not get as high at today’s low biases and in addition the phenomenon of volume inversion tends to keep the stream in the center of the channel away from the surface, due to size quantization.  The other possible degradation mechanism is through electron-hole pair generation by impact ionization, which becomes even less likely due to the low bias, keeping most electrons below the ionization threshold.  This was a problem in older generations of MOSFET with several volts of bias applied.

The main reliability issue to consider for FinFETs is heat.   You need a certain current to flow in the channel for the circuit to work according to specifications, as well as a certain speed of operation.  Since current is charge per second, to increase the current either you increase the channel concentration (for instance increase the cross-section and/or the doping, both of which create undesirable problems) or you make the carriers go faster as hot electrons (you never establish the saturation current that you see in bulk material because channels are very short and there is little scattering).  So, from this perspective, hot electrons are beneficial because they are intrinsically faster (the so called velocity overshoot phenomenon).  They are also always there in a FinFET at normal operation conditions.  The true limitation is that the accelerated electrons gain energy and that energy has to go somewhere.  When the quasi-ballistic electrons reach the drain of the FinFET, energy is released primarily in the form of optical phonon emission.  Optical phonons do not move much because they are associated with low velocity and need time to decay into acoustic phonons through anharmonic processes (acoustic phonons move faster and propagate the thermal energy away to the heat sink).  This bottleneck causes the formation of a hot spot at the drain which is the main reliability problem for nanoscale MOSFETs in general.  The geometry of the FinFET makes it more difficult to syphon the heat away because there is more oxide surface for the same volume and oxide does not absorbs the heat flux.   To limit the formation of heat you can reduce the frequency, modify the duty cycle of the waveform, or reduce the voltage to the extent allowed by the sign-to-noise ratio.  Otherwise, the only other way is to make the channel even shorter so that not as much energy is gained in the traversal, but we are already reaching feasibility limits.  Reducing the size of the channel increases the device density which may not decrease the amount of heat generation per unit area and thermal reliability may remain a problem.

You can reduce the supply voltage and probably use a long channel device. This should reduce the hot electron effect.

Thank you for your answer. But isn't it that the finFETs were fabricated to counter the short comings of the short channel planar devices and counter the Drain Induced Barrier Lowering due to short channels and high drain voltages? Since long channel devices will take a hit on the Silicon real Estate, we, may be, are more likely to concentrate on short channels.

Thank You!

This article may help:

IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 8, AUGUST 2005

Hot Carrier-Induced Degradation in Bulk FinFETs

Sang-Yun Kim and Jong Ho Lee

This one too:

"Origins and implications of increased channel hot carrier variability in nFinFETs", B. Kaczer et al., IRPS 2015