We have a 'datapath' from one CPU, see attachment figure. If the next instruction address is in 'PC Register', how many 'clock cycles 'need to follow 'word add' instruction fetched and executed?
Memory is 10-bits and each instruction at least is 2-words. All register is 10-bits and has 'INC (increment), CLR (clear), LD(load)' instructions. 'Addr' means direct addressing. Onstruction will work on 10-bits word:
Wadd (src1), (src2), (dst)
My instructor solved that it's on a 15 clock cycle. Any hint or idea on how this is calculated?
My try is attached via the attachment figure, but I don't know whether I'm right.
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