If the controller has an integrator (contain a pole in origin), the steady state error is zero for a step input (if the plant does not contain a zero in origin).
you can refer to "Power System Analysis"book written by Hadi Saadat. I think it can help you
using mathematical formulation we can derived it and for step steady state will zero.
It is very easy to caculate the steady-state error (resulting from a step input) based on the "Final Value Theorem":
Step response g(t) for t approaching infinite is identical for setting s=0 in the closed -loop transfer function H(s).
Thus, you can compare different transfer functions (with different controllers).
Consider a system with a control input d(s). Let us say you have designed a controller Gc(s) to meet your system specifications. This controller produces the control input of your system. Any system loop gain is finite. So, to produce a steady control input there will be a finite steady state error (d(t)) = E(s)*G*Gc*H). If you draw the signal flow diagram of such system, the error signal is E=R/(1+G*Gc*H), where R is your reference input and G is system transfer function, Gc is controller transfer function and H is the feedback gain. Basically, steady state error is DC value. If the G*Gc value at DC(zero frequency) is very high that gives a small steady state error. Ideally an infinite dc gain can result a zero steady state error. If you have a pole at origin in your G*Gc*H loop gain, it provides infinite gain at zero frequency. So, the steady state error will be zero. In other words, if you have very high loop gain, very small steady state error is required to produce the control iinput d(s).
This is a classic problem of regulation. You can find some details in a lot of manuals
E.g. In French; the link to INSA web page :
http://docinsa.insa-lyon.fr/polycop/download.php?id=160162&id2=1
See the third page of the document:
http://seit.unsw.adfa.edu.au/staff/sites/valu/teaching/ct2/steady-state-errors.pdf
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