Hello sir/mam
i am using Cadence virtuoso design tool
i have generated symbol of CNTFET ( n and p type) as per Standford compact veriloga code by NCFET_L3.va
then i designed inverter.
I want to ask you >>
1. there are five terminals Gate, Drain, Source, Sub and couple node.
i have shorted to Couple Node and Sub ,,>>>for nCnFet connected to ground via source and for pCnfet these terminal connected to vdc via Source
Is it correct?
2. Next i got accurate transient response but when i start to plot for power consumed of this inverter then i am getting no curve just straight line over 0 zero.
Help Me please.
the best and easiest way to implement inverter usning CNTFET is with Spice Tool. secondly , you have to call only only four nodes in your circuit leaving spatial dependence. Rest is same as in CMOS. Further you can use predictive models instead of stanford.
How to use predictive models in cadence virtuoso tool? please explain sir step wise step
Dear Kumar,
You are utilizing the older version of Stanford compact model for CNTFET transistors. This model is based on numerical calculations and consumes a lot of run time !!. Therefore, I recommend you to utilized Stanford Virtual-Source model for CNTFET transistors. This model is implemented with Verilog-A Language and it is very compatible with HSPICE, CADENCE and ADS. I have utilized this model for three years and no failure has been observed during execution.
For more information, You can reach me at :
Whats app:
+989125725809
Email:
Best Regards.
My circuit of CNFET has no errors but says that simulation is unsuccesful. Please help.
is connecting couple node of pcnfet to the source is correct
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