Dear Abdul kaium Mia,

Could you please sketch a diagram to show your device layout? It looks like that you need put an extra dielectric layer to reduce the leakage current.

Thanks for your response.

Here I have attached the schematic representation of the measurements. For the first one, I have used silver paste to have the bottom contact

And for the second one I have scratched the surface SiO2 and photoresist before making contact via thermal deposition So I can get the Gate contact.

Hello, thanks for the nice diagrams.

You mentioned that your gate current is equivalent to the source current but not drain current. It is likely that your connections cause the problem. There are many references you could find that how to connect your FET to a semiconductor analyser equipment. If you use two SMUs, then the connections for two SMUs should have a common ground.

Actually in ideal case gate current needs to be zero so the drain current equal to source current.

But I am getting gate current is equivalent to drain current. As a result of this drain current is not equal to source current since (Id =Is +Ig)

Note: gate current is equivalent to drain current. And well standard n-type material WS2 grown by CVD methods showings p-type behavior.