Thank you Mohamed, to be more specific a switching pattern for 4 switches per phase may alternate between the following three possibilities:

Switch S1 S2 S3 S4

pattern #1 1 1 0 0

pattern #2 0 1 1 0

pattern #3 0 0 1 1

As far as I know that a standard PWM channel in a DSP controller can affect two specific pins (one is actively controlled, the other is a complement and a dead time is inserted). I can see that S1/S3 can be a complemented pair and S2/S4 is another complemented pair. Therefore I can use two PWM channels for these two pairs, let say PWM1 for S1/S3 and PWM2 for S2/S4 and I configure pins driving S1 and S2 as actively controlled signals and those for S3 and S4 as the complemented signals for S1,S2.

This will work fine for implementing pattern #1 (i.e. it will control the timing of the four switches properly)

When we come to pattern #2, S3 becomes the one that needs to be actively controlled and S1 to be complemented !!! (should I keep the prescribed pin configuration and get the duty for pattern#2 as "100% minus desired duty"?)

When we come to pattern #3, S4 becomes the one that needs to be actively controlled and S2 to be complemented!!! (should I keep the prescribed pin configuration and get the duty for pattern#3 as "100% minus desired duty"?)

I hope that I explained the difficulty I am facing

Dr. Mohamed, do you have any SIMULINK block that implements the SVPWM for three-level inverter NPC or 3LT2C?

After some days of work I could implement the SVPWM switcher for three-phase three-level inverter (NPC or 3LT2C). The implementation is based on maximizing the usage of the knowledge gained from two-level SVPWM. In this implementation, the whole voltage space vector hexagon is divided into six (overlapping sub-hexagons). Each of them is manipulated (by choosing the appropriate switching vectors that ensure similarity with the 2-level standard hexagon) and therefore, each sub-hexagon contains six sub-sectors. Hence, we get 6*6=36 distinct zones, each of which has its own set of control laws for the dwell time of the main six switches of the inverter (the other six are complements).

Since the sub-hexagons are overlapping. An easy differentiation method is based on non-overlapping area of each sub-hexagon and these can be achieved simply by checking the three- phase voltages polarity with respect to zero (these are six areas in turn)

The method is derived from a published Application Report from Texas Instruments (SPRABS6 – October 2012)

For the sake of supporting whoever in need for a straight forward implementation of three phase, three-level SVPWM, I attach here two files, a PDF file that moves gently along the fine details required to develop the 36 control laws of the dwell time to help understanding the development cycle. Also I attach a SIMULINK model that tests the SVPWM switcher block in a setup comprising T-type converter with inductive load.

For those who are interested (invitation goes to Prof. Mohamed Azab as well) , I need to cooperate with those who have the knowledge of voltage balancing of this type of inverter to improve the implemented switcher and arm it with the voltage balancing mechanism. Without voltage balancing, the practical value of the proposed switcher is sure impaired!

After some additional days of work I could seamlessly integrate a neutral point voltage balancing mechanism in the algorithm through redundant vector swapping (redundant vector are those different space vectors that can be used to achieve the same poles voltage, swapping means alternate usage of these redundant vectors to realize the reference space vector). A simulink model (made with Matlab 2015a) compares the performance of the SVPWM with and without NPV balancing is attached. The method of redundant vector swapping is based on this reference:

J. H. C. H. C. Seo;, “A New Simplified Space–Vector PWM Method for Three-Level Inverters,” IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 4, pp. 545–550, 2001.

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