My understanding is that it depends upon the software. If software handles the faulty prefetching misses to recover from error and do error related work, it is faulty. If the software handler is implemented in a way that it ignores the prefetching misses and replace them with nops. then it is non faulty?
Any ideas and related sources will be useful
TLB ==> Translation Lookaside Buffer? If so, for the HW architecture(s) that I am familiar with, SW is unaware of a TLB miss and has no involvement. Also, prefetch of instructions has no SW involvement at all -- this is a purely HW function. The net result of either a TLB miss or a prefetch failure is a decreas in MIPS. This is typically observed when a change in context occurs -- the machine execution slows down while the various caches, TLB, and pipelines are repopulated. This can, of course, be mitigated with a branching pipeline design but it can never be eliminated.
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