I want to implement a circuit in Verilog but one of its inputs Is n-bit and based on that input the number of instantiated modules will be vary, so can I create an array of instances that its size will be calculated based on the width of the noted input ?? or are there any ways other than using arrays to do that at all ??
You can use "Generate for loop" for creating multiple instances
Look for this link form more explanation
http://www.fpgadeveloper.com/2011/07/code-templates-generate-for-loop.html
or look for the attached file
you will find many resources for this function on internet
Good luck
Most simulation, synthesis, and other tools now support the "generate for loop" that's already been mentioned. The alternative if you have older tools is called an "array of instances." It looks something like this:
parameter N = 8;
output [N-1:0] dout;
input [N-1:0] din;
input [1:0] cntl;
mysubmodule [N-1:0] sub_inst (.Z(dout),.D(din),.C(cntl));
For this example, assume the submodule's Z and D are single bit and C is two bits wide. Connection signals that are the same width as the single instance port width (C in this example) are connected together to all instances, while those that are different (i.e. wider) are bit sliced to each instance. So this example unrolls to the equivalent of the following:
mysubmodule sub_inst0 (.Z(dout[0]),.D(din[0]),.C(cntl[1:0]));
mysubmodule sub_inst1 (.Z(dout[1]),.D(din[1]),.C(cntl[1:0]));
mysubmodule sub_inst2 (.Z(dout[2]),.D(din[2]),.C(cntl[1:0]));
etc...
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