Dear Hardware Community,
I am starting my Master Thesis and I would like to explore certain hardware structures and create accurate, parameterized high level models for it. I still haven't decided aon the details of my work and in this formative stage I would like to ask the community for useful resources.
A number of papers that I browsed so far are 5 to 10 years old and I am curious about the most up to date items.
I would also like to ask which kind of tools are commonly employed for power consumption estimation (both low level and high level).
Any information would be much appreciated.
Yours,
Marcin Rutkowski
Dear colleague,
maybe, you can attend the PATMOS conference on early September this year:
http://www.itiv.kit.edu/patmos-vari2013/ This is the 23rd one of the most important international conference series on low power design and implementation, also see: http://hartenstein.de/PATMOS/
Best regards,
Reiner Hartenstein
It depends, what platform you will use. I have worked on Altera FPGAs. In Quartus, you have Power Play tool for power measurement. Similarly, there are other packages in Cadence ans Synopsis as well. You can use such options for comparison purposes with your approach. I think, it will be more clear, once you decide your framework/design platform.
Maybe, you will find some answers in this
https://www.researchgate.net/publication/232551825_Power-Efficient_Tightly-Coupled_Processor_Arrays_for_Digital_Signal_Processing_(PhD_thesis)?ev=prf_pub
Thesis Power-Efficient Tightly-Coupled Processor Arrays for Digital...
Dear Dmitrij,
Thank you for your input. I am going to study you dissertation carefully as it contains a lot of valuable content. It is a significant guidance at this stage of my research.
Yours,
Marcin
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