There are three nMOS transistors connected in series. The gate input is at 5 volts, and the input voltage to the first nMOS is also 5 V. What will be the internal node voltages and why.
I don't think you have provided enough information. what are the gate voltages of eack transistor and what is the voltage on the drain of the top MOST?
The current is the same in all MOSTs so the drain-source voltages will set themselves at a a level to ensure this happens. However, note that the VDSs won't all be the same (as noted in the previous answer) because the VGS's will be different. Also, if all the substrate contacts are connected to ground, you will have effective substrate biases on the top 2 MOSTs which will shift their thrshold voltages. Quite tricky to calculate/estimate all this - why not put it into SPICE ?
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