1.https://publons.com/researcher/1781175/ramesh-kumar-vobulapuram/publications/

2. IMPLEMENTATION OF BCD ADDER USING CLOCK GATING

IJISET.

GOOD WORK MADAM.

https://www.researchgate.net/profile/Sundara_Kumar_V/post/Does_any_FPGA_contains_DEMUX_in_side_as_basic_building_block_as_it_has_LUT/attachment/5eae758ff155db0001f922c7/AS%3A887012479471616%401588491663074/download/ronak-phdthesis2016.pdf

Aparna Sathya Murthy Thank you for your reply. I already have Modelsim, but it won't calculate the processing time of the digital circuits as per my knowledge. Would you please suggest how to calculate the processing time of a digital circuit, for example, an inverter if it is possible using Modelsim?

Sundara Siva Kumar v Thank you for your reply. I am not able to view one of the two pdfs you shared with me. I can download the journal paper but I could not find the answer to my question in that. I just want to know the time taken by the 2x1 mux, 8x1 mux, 3x8 decoder, and inverter (NOT gate). It would be really helpful if you can give me these values provided you have access to any synthesis tool.

The processing time mainly depends on the application and type of the code and your platform in cadence.

Here i am attaching the one example of the work in h spice.

please refer it.

Please share your Views to

https://www.researchgate.net/post/Modern_Engineering_Research?_init=1&_sg=2zgSu1b5dnE_ehz1QKT-RwuuLVoL2ggVfBPM23lqYvoru637Alr6nZkvn2SQ3nLhCo5TBLUgfbngOoHWsgoCLx71c9U.zhkMlazT0rPgICXNQIJUrvT5Snl1YYO0s4PgOc2SDNR45eBMSjHF44m49DF93IF3pahRVwlrZH486HZUoq0mzw

So much confusion...

First things first: Cadence and Synopsys are companies, they are not tools. The tools you are probably referring to are called genus and DC.

There are free synthesis tools like ABC ( https://people.eecs.berkeley.edu/~alanmi/abc/ ) but they are *academic*, so don't expect the same ease of use or same file formats you are used to.

The easiest solution for you would be to do remote login to your university machines. Ask around, this option might be available to you.

I don't see how you can get the information you need from papers. I would not waste time on that. It is not only the tools that you need access to, you also need access to cell libraries. It is the library that determines the performance (to a large extent).

Since you're from Malaysia, you should/could ask your university to access the EDA tools at

http://www.cedec.usm.my/index.php/ms/our-services/eda-1

Currently, many students access these tools remotely.

Samuel Pagliarini Thank you for your response. Yes, the tools I am referring to are genus and DC. Pardon the silly mistakes I have made in asking the question as this research area is new to me, and I have never used the tools before. I have planned to conduct my experiments on hardware but due to the current situation, I do not have access to the lab. I would try to use the free software you have shared, thanks for that, as my university does not have any synthesis software nor they are planning to invest in it in the near future. I was trying my luck here to find the delay of a few digital components to conduct theoretical calculations and write a research paper.

You might want to check academic libraries then. There is SAED 90nm, nangate freePDK 15nm library, and a few others.

Samuel Pagliarini Thank you, I will check these libraries

Arjuna Marzuki Thank you for your reply, I will check with my university regarding remote access to EDA tools.

Samuel Pagliarini mentioned ABC, but ABC is focused in combinational optimization and is largely used to develop new logic synthesis optimizations. Yosys ( http://www.clifford.at/yosys/ ) implemented an almost complete behavioral verilog parser and has ABC as one of the optimization engines. But as he said, you also need a cell library. The FreePDK 15 nm he mentioned, you can get access through Si2 ( https://si2.org/open-cell-library/ )