Hi Ali,

I think three cases can be distinguished:

- Trace in the near field of the source of interference, capacitive coupling (rather a rare case): The coupling becomes weaker with decreasing width (and hence decreasing capacitance between trace and source) of the trace; additionally, comments after the third case apply.

- Trace in the near field of the source, inductive coupling: The trace width has virtually no effect on the strength of the coupling. The distance between the trace and the GND plane (if any) or neighboring GND traces should be as small as possible in order to minimize the magnetic flux between signal trace and GND; see comments after the third case.

- Trace in the far field of the source = incident radiation: The trace width has virtually no direct effect.

If interference problems are to be expected, the best solution would be a coax line; on a PCB, the solution nearest to coax would be a trace between GND planes, with neighboring GND traces on the same layer.

The second best design is a trace over a GND plane, with neighboring GND traces on the same layer.

At least, the area enclosed by the signal trace and the return path (GND) should be minimized as mentioned for the second case.

In most cases, the information of the signal is represented by its voltage (referenced to GND). For a given coupling strength to the source, the interference will decrease with decreasing impedance of the signal path (voltage divider principle). So, in the second and third case, a wide trace would be better than a narrow one. An alternative is a resistor between signal and GND, located at the receiving end of the trace. Of course, the impedance has to be high enough not to overload the signal source; and the additional resistor contributes to the power losses.

If the signal is a digital one (like a gate signal), in most cases you don't have to worry about interference because the difference between "low" voltage and "high" voltage is some hundred millivolt. In digital high speed circuits, where the (undesirable) coupling between different signals might be critical, differential signals are preferable for several reasons.

Adding to the colleague above, I would propose to shield the critical parts of the circuit against the interference by near or far electromagnetic radiation sources. This can be accomplished by using ground planes.

The other solution may be to use balanced wire system such that the common mode signal will be cancelled.

The last precaution is to reduce the impedance level in the circuit such that any induced current will affect little or negligible voltage.

Best wishes

What 'gating signal' e.g. is this signal to the MOSFET gate?

Usually, what matters most is the signal's return path ( the ground plane).

Capacitive pickup to traces usually only matters in RF or high impedance analog design or design involving high pulsed power. The best technique then is to shield the sensitive track by 'burying' it in the inner PCB layer, or at least having decent width of ground plane separating it from the 'aggressor' track.

Note that sometimes the whole PCB ground plane may 'bounce' against enclosure or surroundings thus causing capacitive pickup to all tracks.

Also, when using DC/DC converters with unshielded or even shielded inductors one can see strong magnetic coupling from them. Beyond proper component placement that may be suppressed by using several solid ground planes and on-PCB shield caps.

Thank you for the thorough responses, gentlemen!

Critical Signal Traces on a PCB Layout using Narrower because each connection in between I/p to o/p in PCB nano wires present, that wiring signal output is conditionally waves.

The answers in this thread are quite interesting. I'll propose a different approach that is based on PCB industry standards.

If you're designing a controlled impedance board, you need to balance the width with the other geometric parameters to hit your target impedance. This is basically an optimization problem; if you make the trace width too large, your impedance will be too low, although you can carry more current. Make the trace width too small, then you can pack more traces into a board, but your impedance will be too high and you may have problems with high crosstalk and ringing. Take a look at one of my blog posts on this topic to learn more:

https://www.nwengineeringllc.com/article/optimizing-pcb-trace-width-for-low-inductance-and-current-requirements.php

If you're not designing for controlled impedance (i.e., if your traces are quite short or you're working with DC), then you need to design to meet IPC2221 requirements on trace spacing to prevent ESD. You also need to design traces to carry the required current without heating up too much. You'll have some freedom to choose the trace width in this case because your trace impedance doesn't matter any more; all that matters is any impedance mismatch between sources and loads on an interconnect. You can read more about the proper spacing and trace width in two of my articles for Altium:

https://resources.altium.com/pcb-design-blog/pcb-trace-width-vs-current-table-for-high-voltage-design

https://resources.altium.com/pcb-design-blog/using-an-ipc-2221-calculator-for-high-voltage-design

Depending on the signal frequency (DC, clock, ...etc.) and type (voltage or current). Accordingly you see whether the signal is sensitive to capacitance (narrower is lower coupling capacitance to ground and vice versa), resistance (narrower is larger resistance and vice versa), or inductance (narrower is larger inductance and vice versa).

Hi Ali,

GND plane must be placed nearest to the critical signal trace in order to minimize noise from electromagnetic source. For example differential pair signals (critical signal) must be route on the layer very next to the GND plane or nearest to GND polygon in the same layer to avoid noise interference.