I am working on FPGA and constructed a barrel shifter in .bdf (block diagram/ schematic file). I have used the DE2 115 board. A barrel shifter shifts the data logarithmically; to shift n-bit data, log n (base 2) stages are required. For example, for an 8-bit barrel shifter, 3 stages S2, S1 and S0 are required which can shift the data by 4 bit (or no shift), 2bit (or no shift) and 1 bit (or no shift) respectively. The combination of stages can shift an 8-bit data from 0 to 7 bits. The shifter is designed by using 2x1 Muxes with 3 stages, 8 mux per stage and the shift amount is given by the select lines of each stage.

In my design, I have connected the 8-bit data (to be shifted) and the select lines S2, S1, and S0 (to provide the shift amount) with the switches on the FPGA board, and the output (i.e. data after shifting) is connected to red LEDs. Now I need to calculate the time taken by the shifter to shift the data as soon as I flip the switch position. I have tried using DSO to calculate the timing, Channel 1 of DSO connected to one of the switches used for select lines ( S2, S1 or S0 ) and Channel 2 of DSO is connected to one of the LEDs used for output. The expected outcome was:

If the time taken by a single stage of shifter is "t", then the time taken by two stages would be "2t" and time taken by three stages would be "3t". However, when I captured the waveform on DSO for different stages of shifter, it is showing a constant time for all the stages.

i) To shift an 8-bit data by 1 bit, a single stage would be used. (Flip only Switch S0 from off to on, S1 and S2 are off)

Channel 1 of DSO connected to S0, Channel 2 of DSO is connected to LEDR0. Only one stage is used. The time difference between flipping S0 input and changing LEDR0 from 0 to 1 is around 20ns.

ii) To shift an 8-bit data by 2 bit, a two stages would be used. (Flip only Switch S1 from off to on, S0 and S2 are off)

Channel 1 of DSO connected to S1, Channel 2 of DSO is connected to LEDR0. Two stages are used. The time difference between flipping S1 input and changing LEDR0 from 0 to 1 is around 20ns. It was expected to be approx 40ns.

iii) To shift an 8-bit data by 4 bit, a three stages would be used. (Flip only Switch S2 from off to on, S1 and S0 are off)

Channel 1 of DSO connected to S2, Channel 2 of DSO is connected to LEDR0. Three stages are used. The time difference between flipping S2 input and changing LEDR0 from 0 to 1 is around 20ns. It was expected to be approx 60ns.

I assume that this constant delay is a predefined delay, and if I can use something to constraint the synthesis tool to not optimize the design and to keep every logic element in the schematic entry as a separate logic element on its own in the final implementation, then maybe I will be able to capture the time taken by each stage of the shifter. Could anyone please suggest whether my approach is right or not?

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