We are trying to "evaluate interconnect power" of on-chip memory in NoC.
Can I evaluate power/Testing power for NoC by measuring the interconnect length (accessing data from Core to different cache levels).
I need help to resolve two issues.
1. Can I use the word "Length" to access data from core to different cache Level.
2. Do I use the term "Evaluate power" / "Power testing" or any other term you suggest.
if by length you refer to the topological distance from the core to the level where the data is, or the base latency to reach that cache level, this would be a simplistic metric that assume there is no network contention. Besides, you should also consider the network interface cost as part of the access time.
This metric may be ok to do some initial mapping, i.e. decide which node to locate data to increase locality of reference, but not good to evaluate the network design.
A common term to discuss power constrains is power efficiency; you can calculate the energy delay product.
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