Shahnawaz Talpur

8 Questions 6 Answers 0 Followers

Questions related from Shahnawaz Talpur

Can we use the term "interconnect length" for accessing memory from core to cache levels to access data?

We are trying to "evaluate interconnect power" of on-chip memory in NoC. Can I evaluate power/Testing power for NoC by measuring the interconnect length (accessing data from Core to...

26 May 2014 6,625 1 View

Can someone suggest some papers on 1000-core processor with on-chip network (on-chip memory), but not on optical network?

I am working on multicore, many core, I am stuck in finding some reference work with 1000 cores on-chip network (on-chip memory). I found one paper: "1000-core cache-coherent processor with...

22 May 2014 4,100 4 View

Can anyone suggest me some article to evaluate power for links between Router to cache (L1,L2, L3) in NOC?

Can anyone suggest few research article which evaluate power in NoC interconnects, evaluate power of links between Router to cache (L1,L2, L3) in NOC?

10 May 2014 7,068 3 View

Analyzing Pipeline efficiency. can anyone suggest an easy way? Any links to download Object oriented C++ code?

Any Simulator easy to use with object oriented programming code for Analyzing pipeline efficiency? Suggestions of good papers regarding the above matter? Hardware pipeline. I follow the same...

24 May 2013 10,012 5 View

What factors should be considered to calculate L1 Cahe size

I want to calculate cache size in our design. Instead of cache block/ cache line size, we use the term Ts (Transactional Slice) which may consist 5 instructions. There are two factors in my mind...

04 April 2013 6,481 0 View

What should be the mechanism to fetch data from L2-to-L1, when branch prediction occurs?

I need some suggestions as to what should be the instruction fetch mechanism if I don't use branch prediction.

12 December 2012 6,210 0 View

How to build SPEC2006/CPU2006 config file

I tried but couldn't build .cfg file according to my system. I saw results but all used Intel compiler but I am using MS visual studio 2008 compiler. My Operating systems in windows 7 32bit ,...

08 December 2012 1,045 1 View

Can anyone recommend a mold for creating a "Theoretical Analysis Model" for Cache?

I am working with Mutlicore CMP. My research topic is on improving cache efficiency. I am establishing a model to verify the cache size in The Architecture TriBA. Which modeling technique should I...

11 October 2012 6,423 0 View