good luck

It might be possible that you need to burn in conductive pathways in the OTFT before usage. In that case attempt to do several voltage sweeps  before measurements.

The current is quite low, but you did not mention about the size of channel. With Sonoplot its length is rather close to or higher than 100um, but even though with TIPS-pentacene you should obtain 10-5A in 1cm wide channel.

In my opinion you have started with too many things that can go wrong. I know from my experience that one should start with most simple system. If you can try to make OTFT on inorganic substrate (i.e. silicon with SiO2 dielectric and metallic, evaporated S and D electrodes). Spin coat TIPS-pentacene and measure the characteristics.

Make some tracks of your nano-ink on, e.g., glass and measure conductivity (after, of course, thermal treatment). If it is OK (and I know that with 150C treatment it is sometimes not), build for example OTFT in BGTC configuration, spin coating TIPS-pentacene on Si/SiO2 substrate and the plot SD electrodes using your ink. Actually I made such transistors using p3ht and PEDOT:PSS plotted with sonoplot and they were working OK. You should also check the continuity of tracks under microscope.

You should also try separately the quality of your dielectric (e.g. making planar capacitor).

If you are sure about each part, built the whole OFET.

It requires some time, but you will learn a lot and troubleshooting will be easier:-)

Dear Krzysztof Janus,

thank you for your helpful answer, i will as you recommend.

Try to flip the stack and make top gate, it is easier. Have you done this with a different dielectric? Also your dielectric at 60nm is extremely thin for most conditions and is calling for defects. In practical lab conditions you might need >500nm. You need to measure thickness directly/indirectly to be sure your gate dielectric is OK.

thank you for your helpful answer, i will do as you recommend.

I agree with Krzysztof and Janos:

1. Test/benchmark your TIPS-pentacene on Si/SiO2.

2. Try bottom gate devices with much thicker dielectric > 500 nm . How thick is your bottom gate? What is its roughness? Check if edges of the printed ink are not rough. Personally, I doubt that 60 nm of PVP is going to fully cover your silver track (gate). Then if it does not work, try top gate devices - it might work better if you have shorts due to poor coverage quality of your dielectric because you will deposit your insulator after the deposition of TIPS-pentacene. Can you print on cross-linked PVP?

3. If it does not work, try different dielectric (Cytop? PMMA? with min. 1 micron thickness).

Good Luck!

Dear Leszek, I can't print cross-linked PVP so, I will increase its thickness.

I tried top-gate once: the solvent of the dielectric dissolves the deposited Tips-pentacene layer, so it didn't work with me.

thanks.

You are right, top-gate OFETs are tricky to fabricate because you need a compatible dielectric solution, e.g. Cytop, which does not dissolve your semiconductor layer. These pre-formulated insulator solutions (such as Cytop) tend to be quite expensive (~ £1000 for 1 litre) and are difficult to get.

In point two, what I meant is if you can spin-coat PVP (min. 250 nm, but preferably > 500 nm), cross-link it and then print your silver gate electrode.

Also, you should try to modify your S-D contacts with PFBT SAM and blend TIPS-Pentacene with high molecular weight (~100,000) poly(alpha)mehtylstyrene (or just polystyrene). You should get much better device performance and reproducibility.

I  don't have the resources to get PFBT SAM, but i can blend TIps-Pen, thank you