I can suggest you some improvements:

1. Try to coat backside of  Si with Au and use it as gate electrode.

2. Try annealing to increase the TIPS grain size in the film.

3. Reduce the gate length or Source to drain distance (by the way what gate lengths have you used?)

4. Try higher gate voltages and higher Vdrain. (What gate voltages are you using??? V drain used is small).

Actually it seems that the voltage applied at gate is either too small to create any channel effect or the gate effect is not reaching the TIPS at all.  

From the graphs you attached, I think, your devices are not working. I have several question before giving any suggestions.

1) You did not show your transfer characteristics, i.e., ID vs. VG curve(s). How do they look like?

2) The voltage range is okay? Did you try higher ranges? While measuring transfer curves, what voltage you used for biasing the drain?

Now please note the following-

1) You said your Si/SiO2 devices show the same results, which, if you processing is okay, should work. I don't have much information about film quality seeing your attached images. Did you measure thickness? Usually, spin-coated TIPS-PEN films show very poor performance, as you cannot form TIPS-PEN crystals. But drop-cast film should be good.

2) First optimize your processing for Si/SiO2 substrates; once you get good results, you can try HfOx dielectric layer.

3) TIPS-PEN is very stable, so don't worry about the processing ambient.

For more information, you can look at our paper here-

https://www.researchgate.net/publication/255774653_High-performance_organic_field-effect_transistors_with_dielectric_and_active_layers_printed_sequentially_by_ultrasonic_spraying

Good luck!

Article High-performance organic field-effect transistors with diele...

I thank both researchers for their interest shown.

I have annealed TIPS PEN film overnight @85 dC. Channel length are  50, 75, 100, 150 and 200 Microns, and width are from 400 to 4000 Microns.

Does taking the gate electrode connection from the back of the wafer affect the performance of the device in any way? What is the logical issue if I take the gate contact from the top as I have shown in the image?

I have tried various Gate Voltages like from -2 to -10 Volts. Normally with HfOx characteristics can be obtained within -5 V (both at gate and drain).

Transfer curve is also absurd. Drain current is not varying much (not more than an order) with 2 to-5 V or 4 to -10 V gate voltage range.

I understand about the poor quality of the TIPS PEN spin coated film, but in the first and second image (drop cast film) crystals can be clearly seen between source and drain electrode.

in addition, I have Si wafer which has SiO2 on both sides. I was etching this SiO2 using conc.HF solution for 5-10 minutes from a single corner ( I am using this corner as the gate contact from the top). But if even a very thin layer of SiO2 is remaining on Si in this area and I am applying gate voltage there, will it create any problem?

I request you to point out the any processing mistake which you think is likely to be committed.

Dear Deepak,

As far as I can see you are using one of quite new Keithley double SMU.  The oscillation you observe are rather not physical (non-conducting channel should give some low-level noise, not oscillations). As I had the same problem with Keithley (output FET characteristics with some oscillations) I can suggest you to check time settings in software controlling the experiment. This oscillations may origin from poorly shielded experimental set-up and may be lowered by setting NPLC value higher or equal to 1. The default value in my system was 0.1 only and it was certainly too low. 

Regarding the gate connection, we are usually using Si(n+)/SiO2 substrates. You can connect to the bottom, to the side of a substrate (with conductive silver paint), but most recently we remove mechanically small part of SiO2 and connecting from the top using gold-plated probe. But this is the same as connecting from the top to the area protected from HfOx, as you do.

And I will also suggest to follow previous advice of testing the system on well defined substrate. First try to build FET with well known and tested substrate, then try to make your own dielectric.

Hope it helps,

Krzysztof

Dear Deepak,

I agree with Janus, this type of oscillation (in my case) come when your probe tip is not good or your have not made a good contact with probe to your device.

About putting gate at top, assuming your material is patterned in such a way that it is not in contact to gate electrode, this may not be a good idea. U may put the silver paint (as janus said ) on this but assurance of good gate contact is a not guaranteed. best to go for back metallization.  We have tried using the method of top gate contact, initially it gave good transistors characteristics but later it went bad , repeatability is a not there.

Can you characterize your device in dry N2 environment (like glove box) or in vacuum. Try annealing in vacuum at  < 75 C (50 C is good ) if possible, you can flow N2 on your device while characterizing.

One more issue is solvent, (i do not know what u have used), it is already reported transport in organic (mostly polymers ) depends on type of solvent too.

As everybody said, try growing your material on well reported oxides like SiO2, Al2O3

Hope it helps

I sincerely thank Janus and Sanjoy for their valuable suggestions.

I am using Keithley 4200 SCS for measurement with KITE software. I also feel that characterization setup is not shielded. In the software, timing options are there which include hold and sweep delay and speed options. The speed option further contains delay factor, filter factor and A/D aperture time (unit of this is PLCs). I have seen the effect of delay factor that with more value of this factor, results are less oscillatory. But about rest two factors, I don't have any idea. In my general measurements NPLCs were auto (I don't know the number). But as you suggest, I guess, I need to adjust this factor also.

As everybody is saying that they opt for back metallization or back contact, I guess, I would also have to go for this. But reason is still unclear.

Also, which option will be better?  Connecting a Cu wire on bottom side with Ag paste or pasting a long conducting Cu adhesive tape which extends out of sample?

I will definitely make devices first on Si/SiO2 now, as suggested by everybody.

I am making my solution in Toluene. I can definitely make N2 flow arrangement while characterizing. I will also try vacuum annealing.

Also, is there any simpler way to probe on Au contact devices, as when I am trying to bring the tip in contact with Au surface (thickness ~100 nm), either it is not in proper contact  or in the next moment it pierces through the Au film?

Will it be fine if I put Ag paste on Au contacts?

Dear Deepak,

Does the probe really pierce through a gold of 100nm?

While making contact, one should not push the ( tungsten ) probe too much, it may damage the probe tip, which in future cases may be a reason of poor contact.

When u move down the probe, just make sure it scratches (slides) on gold film. a small scratch is assurance of good physical contact b/w gold and probe tip.

Using silver paste on Au contact, assuming it remains soft through out the characterization, you can definitely try that and do report , i would like see.

One more thing , before putting the pentacene on it, can you do I-V and C-V of the Silicon MOS to see if contact is proper and leakage current through.

Taking the contact from top or bottom is one or the same thing. But, even on the top you must coat Au for proper gate contact. 

Its easier to fabricate the Au contact at bottom, because practically while etching the oxide from top to form the Gate, the HF fumes may damage the other part of the oxide layer even after photoresist protection and may make it leaky. 15-20 min are more than sufficient to cause such damages. Therefore, back side contacts are preferred.

Do the grounding of Gate and source contacts properly during the measurements. For 200nm SiO2, you may have to go to voltages as high as 40 V to see the transistor characteristics.

Hi, Deepak,

I also had hard time in making a high performance TFT using solution processed CdS inorganic semiconductor as my channel however I was able to make at the end. I had lot of problems with peeling of my layed but it got fixed after aneealing so thing you have also done.

But I would try to characterize your channel layer it self even putting them together to make a device to see if it's highly conducting from there we can move forward. HfO2 60nm is about right but again it does depend on you channel thickness and carrier concentration. Take a look at our APL paer attached her and let me know if you have any questions.

Thanks,

Article High-performance chemical-bath deposited CdS thin-film trans...

Hi Mr. Hareesh,

I thank you for sharing your valuable suggestions.

Recently I have been able to fabricate OFETs successfully with SiO2. The only different thing which I have done is to take gate contact from the bottom of the highly doped n-Si, and transistors started working.

The query that I would like to ask is that in some of the transistors shape of the transfer and output characteristics is not proper (for ex. drain current at higher Vgs is lesser than that of lower Vgs). what can be the reason for this anomaly and How can I correct it? While making these set of transistors I allowed the solvent to evaporate gradually without annealing them even a bit.  Although the active material in OFETs is organic, and certainly it is not advisable to give them a heat treatment, But will the characteristics improve if I give them a mild annealing? Also should this annealing be before or after S/D deposition?    

Thanks again for your interest...

Did you have roughness of TIPS-PEN films? because you deposited 60 nm HfO2 if it was rough then oxide wouldn't  fully cover uniform then you will have lot of leakage problem which is why I do see you have (-) ve  S-D current. Try with 500 to 600 nm SiO2 having 100 nm thick  TIPS-PEN film should work.At the same time show us S-D current with Zero gate voltage just to make sure your TIPS_PEN is conducting but very low magnitude I would like to see (micro Amps). Once if they started working then replace with HfO2.

 Let me know if you have question.

Hi Hareesh,

I have TIPS-PEN micro-crystals instead of uniform film on the SiO2 substrate. If you are asking about crystal roughness, then it is less than 2 nm (rms). 

Now transistors are working and S-D current will be -ve as TIPS-PEN is a p type semiconductor. at zero gate voltage drain current is in pico-nano range. But in some of the devices I am getting the problem as described in my previous post (for ex. drain current at higher Vgs is lesser than that of lower Vgs). what can be the reason for this anomaly and How can I correct it? While making these set of transistors I allowed the solvent to evaporate gradually without annealing them even a bit.  Although the active material in OFETs is organic, and certainly it is not advisable to give them a heat treatment, But will the characteristics improve if I give them a mild annealing? Also should this annealing be before or after S/D deposition?    

Thanks again for your interest...

Hi Deepak,

I'm not an expert on TIPS-PEN, so I don't know how thermally stable it is. But as a general information I can perhaps say that organics aren't as bad as you might think where temperature is concerned. I use thermally evaporated pentacene mostly and there's a whole bunch of stuff you can do with it without breaking it: Heating to 100°C for several minutes (or even an hour) is something I do quite regularly and a colleague of mine has even done some Au wet etching on pentacene. The mobility in his OFETs suffered a little, but it still worked. So maybe you should just try annealing your devices, perhaps the slow solvent evaporation does something to the morphology of your layers. To check for that, you could prepare a TIPS-PEN film by your normal method and one with annealing and then check the morphology e.g. by AFM. This may also tell you whether it is better to do the annealing step before or after Au evaporation (depending on film roughness before and after annealing and so forth). Generally though, I would assume that it's best to get the solvent out before you deposit your top contacts. After all, solvent molecules still left in there might do something or other at the contact interface to limit your injection.

I hope this helps a little!

Thanks a lot Alrun and all other for useful information...

I have annealed my devices and found them to be working..

But now I am facing another anomalous issue.

Drain current (At a particular Vds and Vgs) in transfer characteristics and Drain current in output characteristics (at the same set of Vds and Vgs) are not equal.

Drain current in Output Characteristics (Id-Vds curve) at some (Vgs-Vds) is almost 1/10th of the drain current in the transfer characteristics (Id-Vgs) at same (Vgs-Vds).

Can all of you suggest some reasons behind this anomaly and some methods to alleviate this issue?

Thanks...

hi deepak,

Just guessing: have u done these measurements multiple times?

Can u measure Current at particular Vds and Vgs as a function of time?if its decreasing , it may be due to bias stress effect.

Thank You Sanjoy,

But I did measurement once only...first transfer and then output...

If we keep on applying voltage then it will definitely decrease due to bias stress effect..

Hi Deepak,

a lower current in the output characteristics compared to the transfer characteristics is quite normal, but a factor of 10 is probably too much of a decrease. How much time does your measurement procedure leave between taking individual data points and how shortly after the transfer characteristic do you measure the output characteristic?

Thank You Alrun for your response,

I am giving 0.25 secs as sweep delay (delay between measurement of two data points). I am taking the output characteristics just after the transfer characteristics of the device.

try to slow down a little bit and check again.

You may also try to measure temporal behavior of current (at certain U_SD) for a few seconds after increasing U_GS. After each increase of U_GS you are charging capacitor. Sometimes, if the channel current is very low the charging current may influence your measured result. You may also stay with very fast sweep, but add 1-2 sec delay after each change of U_GS.

try to take multiple reading and average them in your semiconductor analyzer