It's possible, but costly. You would have to dedicate a large area with many layers and a very high k dielectric. Try working out the details with this formula:

C= k*Eo*A/D

C = Capacitance

k = Dielectric Constant of the layer between plates

Eo = Permittivity of free space = 8.854x10-12

A = Area in meters

D = Distance between plates in meters

You would need something like 1 square millimeter of plate area with 100 nanometer plate distance and dielectric constant of 1130 to get 100 nF. Vary the values as you wish, it's gonna be tough to dedicate that kind of space and if you get too close with the distance on the plate layers, your working voltage will go down and leakage will go up.

Sanat,

The answer is maybe BUT it really depends on the technology you are using as well as other requirement from the capacitor, working voltage, working temperature, ESR, leakage, etc.

It will require a large area and/or high dielectric material which may not be available or practical in the technology you are using.

If this is for manufacturing, large area capacitors will of course increase the price of the final design significantly AND effect the yield in the fab since larger capacitors are more likely to include a defect.

Thank you Robert C. Baumann. I have very little idea about chip design and would definitely like to know what is the highest capacitance value that can be embedded inside a chip conviniently? Will 100pF be a good value to fabricate?

Metal-silicon oxide-silicon structure is used in IC fabrication. Typical oxide thickness can be 0.001mm and area can be 1 mm*mm. Assuming a dielectric constant of 10, we can obtain, 88 pF capacitor. Further, these parameters can be tweaked to get the desired capacitance in pF range.

Thank you AR Reddy Sir.

Dear Sanat Kumar Mishra,

One more thing is that your should refer to the Process document (in PDK) which shows you the sheet capacitance of all supported capacitor types.

However, the value you want to design is big. So it will be very costly since the capacitance area is large for your desired value.

.

Sanat Kumar:

.

Do not overlook the fact that, real capacitors

exhibit significant amounts of intrinsic series

resistance and inductance,

.

Tell us a little more about the application you

have in mind; we practiced designers may be

able to suggest some alternative solutions.

.

Barrie 

nF is unpractical to be implemented on chip. you can use techniques like "Miller capacitance multiplier" or "alpa block"  to increase the capacitor to K ratio upto 1000. so you can integrate pF and have and effective capacitor in nF.

.

Mohamed:

.

Your suggestion is not quite correct.  There is

no question that one can synthesize effectively

higher capacitances using circuit techniques.

But this is not answer to the original enquiry.

Anyway, "fake" capacitances of this dubious

variety are in no useful way equivalent to an

ideal capacitor of the same value. Please -

never let simple circuit theory get in the way

of sound practical thinking.

.

Actually, it is not hard to create a REAL 1nF

on an IC chip. It has been done for decades.

.

In fact, modern CPUs have as much as 2 uF -

that's TWO MICROFARADS - of capacitance

on a single chip. Here's why:.

.

As one example, the AMD FX 8350 processor

can consumes a supply current of about 100A

at a supply voltage of 1.35V. This amounts an

effective resistance of only 13.5 milliohms. To

prevent  significant supply-line ripple - inverter

gates generate large current spikes - the local

supply must be shunted to the local 'ground'

with real capacitors of significant size.

.

To provide a total, on-chip capacitive reactance

similar in value to small fraction of the effective

net supply-line impedance requires the use of a

very large total on-chip capacitance. Even after

this has been provided, large REAL capacitors

are needed on the PC board. (See attached file).

.

Barrie

Thank you Mr. Barrie for a nice explanation with a beautiful example.

Sanat

your forgot the cost because of the huge area this is why nF is impractical.

Hi All,

Could you please refer us to a source that shows the capacitance values of the different VLSI technologies?

Thanks,

The original question is a bit like asking "How long is a piece of string".

To say "it all depends" isn't much help, either but that's the kernel. How

big a "chip" are you speaking of? What percentage of this available area

are you prepared to use for your total capacitance? (Keep in mind that

the available area must not only account for the active circuitry but also

allow for area consumed by bonding pads and other "dead elements").

If (for some reason; are there are plenty) you need to employ a very large

capacitance, consider using one (or maybe two) package pins. They are

invariably cheaper than using silicon area. Keep in mind that capacitors

using a very thin dielectric may suffer from pinholes that affect yield;

obviously the bigger the capacitor's area, the more likely yield will suffer.

What kind of capacitor do you need? If this is for very prosaic purposes

such as "decoupling" there are several types of junction capacitors you

can consider. Many decades ago Plessey were putting 1nF decoupling

capacitors on RF log-amps. (See also the Intel PDF that I supplied).

Your question needs much more clarity. We on this site can really only

help if all the specifics are fully delineated. But perhaps you are simply

curious, Sanat?

Thanks a lot for your answer.

I simply need to see how power scales from 90 nm to 45 nm, and form 45 nm to 20 nm ( in case of SRAM). I am using ( P = CV2f) to estimate the power consumption of 20 nm SRAM compared to 90 and 45. I used Cacti to estimate the power of 90 nm and 45 nm but when I tried to estimate the power of 20 nm it gave an error ( maybe the 20 nm technology is not supported yet in this Cacti version)

By changing C, V, and f among the different technologies, I am trying to estimate the power scale.

Sorry for the unclear question and I hope this one is better.

U can use capcitance multiplier circuit. There are many different circuit topology in literature. İf you want to help about capcitance multiplier. i can help

Thank you very much Tayfun.

When increasing the amount of capacitance in your IC design, The most important issue is the area that it occupies. In fact, if the area is not an issue, you can increase the amount of capacitance using "multiplier" option which multiplies the capacitor specified by a specific factor.