Structure has to be optimised by carrying out simulation work prior to fabrication. If you could share details of your solar cell structure then I can ask one of my student to find out optimised doping levels and structure of the cell. Good luck 

first optimize junction using dark iv measurement, then optimize the contact resistance. In your case, series resistance is very high. please also check contact resistance.

Have you did any annealing after metallization?

The air-break in your stated process flow is also not the best for efficiency. Try to repeat your clean steps for the second side deposition, this will reduce the series resistance.

ITO recipe can also be problematic.  Ensure that you are doing a pre-sputter on the material before you deposit the ITO.  As Ramachandran A V pointed out, annealing may help with the resistance as well.  The silver evaporation will help some, but typically a longer anneal in an inert gas helps most metal junctions.

Shahzad Hussain sir

p c-Si: thickness 270nm, resi- 5-10ohmcm, double side polished, plane surface (not textured)

i aSiH -5nm, bandgap -1.8eV, p, naSiH -10nm, bandgap -1.85eV, ITO -80 nm, backside Ag deposited by thermal and front Side Ag contacts about 1micron thick.

Ramachandran and Matthew Alan Ring sir , I have annealed in vacuum for 1hr at 150 0C but not much changes almost same. I will try in Inert gas atmosphere. how many hours required for annealing ?? I have deposited cell at 200 0C, shall i anneal at higher than deposition temperature or below the deposition temperature ?

Matthew Alan Ring sir I did not get it this sentence  " The air-break in your stated process flow is also not the best for efficiency " you mean process flow  during deposition ???

Firoz Khan sir, I agree with you that series resistance is high and shunt is low but how to optimize contact resistance ??

and one more thing is that on  front side,  i sputtered ITO on n a Si:H layer into number of cells and made different contacts for each cell, while backside through out Ag evaporated (not number  of cells)(backside only one Ag layer contact for all cells)

using these same deposition conditions I have deposited cell on ITO coated glass, it is showing somewhat better IV curve compare to cell on c-Si substrate.

structure: ITO coated glass/p a-SI:H(20nm)/i a-SI:H (200nm)/n a-Si:H (20nm)/Ag, (commercially purchased ITO coated glass)

see below curve

First optimize the contact resistance on front and back surface. The contact resistance can be determine by transmission line method. For pv cell parameters please see "Determination of the diode parameters of a-Si and CdTe solar modules using variation of the intensity of illumination: An application, Solar Energy 85 (2011)2288-2294.

YOU CAN COAT THE SURFACE WITH APPROPRIATE ANTI-REFLECTIVE MATERIAL. ALSO OPTIMIZING THROUGH VARIOUS ANNEALING TIME AND TEMPERATURE CAN WORK

Dear Venkat,

I believe the attached comprehensive review of De Wolf et al. may help you to answer your questions and direct you to useful sources.

All the best.

Erkan

Article High-efficiency Silicon Heterojunction Solar Cells: A Review

Dear Venkanna,

welcome,

The layer stack which you brought in your question seems me odd and i wonder how it could as a solar cell. The first question is what do you seek/ do you seek single junction solar cell or multijunction solar cell? If you target multijunction solar cell ,your stack must be p+in+p+in+. If you seek single junction stack must be p+in+. This is clear from your second pin cell, it functions more or less properly.

Please stack the layer correctly and you will get working solar cells.

Best wishes