Hello,

could you explain what do you understand by "timing simulation" (For simulation you could use embedded to Xilinx ISE Isim or other pluggable simulation tool like ModelSim, but as I understood, you handled it.)?

However, after synthesys process you could see timing constraints for your design in console (see 1 for ISE Navigator and 4 for PlanAhead). Further, after implementation process in ISE Navigator and generation of bitsream in PlanAhead you could see timings calculated for your chip for every route in your design in timing report (see 2, 3 for ISE Navigator and 5, 6 for PlanAhead).

Dear Dmitriy Kornilov

Thank you for your reply, and I appreciate the screenshots as it helped me to understand the answer better. I will also try to explain my problem with screenshots.

Is it possible to calculate the actual delay of the circuit without optimizing it into the LUT, since LUT is providing a fixed delay of 0.612ns?

I want to calculate the exact delay of a digital circuit at the gate level using Xilinx simulation, therefore, I need to simulate the circuit without optimization. For example, the RTL schematic of the circuit 1.Circuit.jpeg is given by Xilinx as shown in the image 2.RTL.png. The RTL schematic provides a similar circuit as we wanted to implement using Verilog coding. The aim is to synthesize the above circuit with two MUX and four basic gates without optimizing it into LUT. However, the Technology Schematic is providing a single LUT that implements the truth table of the circuit without considering the intermediate digital blocks, as shown in 3.Technology.png and 4.LUT.png. It implements the final outcome Y=S'A'+AB in LUT3 and eliminates the original circuit. The delay is 5.753ns for the above circuit which is provided for the Technology schematic of the circuit with basic gates only inside the LUT3 as shown in 5.Design Summary.png.

Later, I have used the KEEP attribute to stop the optimization of the circuit (6.KEEP.png). The RTL schematic for KEEP=NO and KEEP=YES is the same as shown in the image 2.RTL.png, but the Technology Schematic with KEEP=YES has a different structure, as it optimizes each part of the circuit in a separate LUT, as shown in 7.Tech_Keep.png. Now the design summary for KEEP=YES as shown in 8.DS.png provides the delay of 7.884ns. However, the delay of LUT is fixed to 0.612ns irrespective of the KEEP value or the circuit structure inside LUT.

Is it possible to calculate the actual delay of the circuit without optimizing it into the LUT, since LUT is providing a fixed delay of 0.612ns?

Dear Pallavi you can read this pdf guide for xilinx

Dear Pallavi Srivastava,

During synthesis, ISE will try to minimize the cost of a design entry file (schematic, VHDL, Verilog) using LUTs, because it is the way Xilinx FPGAs works. All boolean functions will be synthesized into LUTs. If I'm not mistaken the KEEP = YES is used when you have a project with multiple design entry files, or even with a single file (for example VHDL), but multiple components, so ISE will optimize each component and translate each component into LUTs. If you use KEEP = NO, even though you use multiple files o single file with multiple components, ISE will treat the design without hierarchy, similar to a flat design, and that's why you get different results. You cannot avoid synthesizing a design without using LUTs, unless you use BRAMs to build the truth table of your design. You may use distributed RAM for synthesizing a logic function (as a truth table), but at the end you use LUTs. Don't forget that basic elements for synthesizing logic functions are the CLBs, and inside CLBs you find the LUTs.

I think that the only way to work without LUTs for synthesizing logic functions is to do direct manipulation of the bitstream (very difficult task), skipping the LUTs and see if other elements inside the CLB (muxes, gates) are able to implement the logic function. 1s and 0s inside a single frame are used to select paths and logic inside CLBs. Unfortunately, I don't think Xilinx ever revealed the exact position of each bit inside a frame to control muxes, etc., in CLBs.

Regards,

Manually adding delays in your Verilog testbench, and manually accumulating propagation delays into non-synthesisable test variables.

The trick is to skip the synthesis step whatsoever, and only use testbench/simulation. You don't need Xilinx for that, Verilator, and other free Verilog implementations can do as well.

The key answer is you need to write code manually; I'm not aware about any magical tools which calculate accumulated propagation delay.

There will also be clock cycle time (the critical path time), and the number of cycles from input data to computed result.

Pallavi Srivastava Xilinx ISE is obsolete now and has been stopped updating since 2017.

You should start with Vivado and run some basic digital systems on Xilinx FPGAs. A very nice repository of digital designs is: http://esd.cs.ucr.edu/labs/tutorial/

These are basic digital systems with their test benches which you will be able to simulate in Free Vivado quite easily.

Hassan Nasser Hassan has shared a document from Xilinx but I won't recommend studying it as a first place to learn because they are quite difficult for a beginner.

Good luck, and happy coding.

@Muhammad Ifran:

I respect your opinion; But the file l was shared is intended by xilinx team for beginners, I even used it when I started learning about this environment.

I am not aware of whether this can be done by Xilinx or not. But the proper way of having design reports in with the actual gates is using "Design Compiler" software which allows the user to have timing, power, area reports.