I am reading about hysteresis comparator below and wondering if a mosfet can be on if vgs is larger than threshold voltage but there is no current flow through it (vds is zero), As you can see in the picture, because M2 is off, there is no current flowing through M6. However, the slide says that M6 is on (active). So could you comment about this?
http://aicdesign.org/SCNOTES/2006notes/Chap08(8_7_06).pdf
Hmmm... Well Huan, let's imagine what happens there...
M6 is the output part of the current mirror assembled by M2 and M6... So M6 is simply a voltage-controlled current source (VCCS) that tries to pass its current through M2...
Since M2 is off (open circuit), no any current flows through it... and M6 begins decreasing its static resistance RDS (and accordingly, the voltage drop VDS across it) to establish this current... but fails... and finally saturates (becomes on)...
So, it seems it is possible for a transistor to be on without current passing through it... Here is an electromechanical analogy - imagine a closed switch is "connected" in an open circuit:) The switch is on but there is no current flowing through it... and the voltage drop across it is zero...
We can observe this situation in many cases from our daily life when we turn on the switch of a power supply but we have forgotten to connect a load to it:)
Hi Huan !
The circuit provided by you is JFET differential amplifier and pair M3&M6 forms current mirror. ultimately serves purpose of high resistance in drain terminal.
DC transfer characteristics of such circuits are formed by normalizing input voltage and output current(ID). These characteristics have linear behavior for some input and then continues to be nonlinear.These characteristics are plotted between ID of each arm (As per diagram IDm1 and IDm2) along Y axis and VGS1-VGS2 along X axis.
In the diagram provided one of the gate is permanently grounded while other gate input will vary between -VGS-0-+VGS. Now you want say that when one of the FET is of and other is on even though it is off how current flows through it. Is that right?
In this case when one transistor is on (example m2 on and m1 off treating other transistors as normal resistor) the ISS (i.e. IS1+IS2) IS1 will be very small and IS2 will be equal to approximate Quiescent current.
Since M3 & M6 forms current mirror, current in IDm3 will try IDm6. This will maintain M6 as active.
Think about CMOS...
The gate voltage will give you an inversion layer but if there is nowhere for the current to flow, VDS will have to go to zero and 'no' current will flow (as mentioned above). Actually nothing is ever zero (except sometimes your bank account balance), there will be a small leakage current flowing but small enough to ignore in this context. (Unless you are dealing with very small devices - look at Moore's Law scaling... )
Thank you, everyone, for the thoughtful answers!
I really like the idea that M3 and M4 are inputs of current mirror and they serve as current to voltage converters. M1 is on, M2 is off so there is some current through M1 and M3 will converter this current into Vsg and this voltage turns on M6. Similarly M2 is off so there is no current through it. M4 will converter this current (0A) to voltage (Vsg = 0V or Vg = VDD) so both M4 and M7 are off.
Could you share some views in how is it a positive feedback here?
As I can see, the inputs of both current mirrors are driven by the outputs of the long-tailed pair... and the output of each current mirror is connected in parallel to the input of the other current mirror... thus diverting a part of its input current. This arrangement functionally resembles the ordinary cross-coupled pair of MOS inverters.
Imagine initially there is an equilibrium: both input voltages (vi1 and vi2) are equal; so the four currents (of M3, M6, M4 and M7) are equal.
Now if, for example, vi1 slightly exceeds vi2, IM3 increases -> IM6 increases thus decreasing IM4 -> IM7 decreases thus increasing even more IM3... So, in this arrangement, a reinforcing positive feedback exists.
Excellent answer! Thank you, prof. Cyril.
I am wondering if there is an intuitive how hysteresis is created in the circuit?
Could you share your view?
Huan,
If there is a positive feedback, there is a hysteresis as well... The reason of this is that after the switching, the element itself changes its threshold...
https://en.wikibooks.org/wiki/Circuit_Idea/Group_68a#Lab_4:_Op-amp_trigger_circuits_with_positive_feedback
https://en.wikibooks.org/wiki/Circuit_Idea/Group_64a#Lab_4:_Op-amp_circuits_with_positive_feedback
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