I am working on a project using the Nexys 4 fpga. My project is image processing using verilog HDL on a vga screen (CRT). I'm having trouble in displaying the image, the output on the screen is shown in image attached. I have tried to modify the hsync and vsync but with no use. We stored the image in the BRAM and we are accessing it using a program counter. Could anyone help??
Note: Sync and counter module can be provided upon request.
Note2 : The image we are using is 320*240
Timing is everything in this case. I'd suggest checking the hsync and vsync pulses using oscilloscope/analyzer to verify if the timing is right.
Besides timing, one thing is make sure you are using the right clock frequency based on the timing format you are using, and also check all the counters for generating the address to read BRAM.
I checked the frequency and it's correct. I think the problem may be in reading from the BRAM because the image is 320*240 and my hsync and vsync work on 640*480.
Try to change your controller to work with 320x240 resolution. Or maybe you should read the BRAM only once.
Thanks for your response :) . The problem was reading from the file, I was reading it pixel by pixel and displaying it as 1d not converting it to 2d to the vga display
here are many solution and this depend on your application.
here for example you can send you image from RS232
http://www.instructables.com/id/Image-from-FPGA-to-VGA/
http://hackaday.com/2011/09/09/putting-laptop-lcds-to-use-with-an-fpga/#content
https://embeddedthoughts.com/2016/07/29/driving-a-vga-monitor-using-an-fpga/
https://www.ijircce.com/upload/2015/july/104_Design.pdf
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