I am working on a project using the Nexys 4 fpga. My project is image processing using verilog HDL on a vga screen (CRT). I'm having trouble in displaying the image, the output on the screen is shown in image attached. I have tried to modify the hsync and vsync but with no use. We stored the image in the BRAM and we are accessing it using a program counter. Could anyone help??
Note: Sync and counter module can be provided upon request.
Note2 : The image we are using is 320*240