I know it's a very general question, but as a "rule of thumb" for a circuit that has a bandwidth of "f":
How much delay is typically acceptable for an IC within that circuit? (for example is 1/10 of 1/f is acceptable as the delay or what?)
Thanks!
Hi Ali Shahabi ,
IMHO, you cannot find such a rule of thumb. Take, for instance, an ECL flipflop (please see attached datasheet): Its maximum clock frequency is 3 GHz, so T = 333 ps, and it's propagation delay is about 340 ps > T. Nevertheless, it's a very useful IC.
I think more critically parameters (which make worst case considerations more complex) are the dependence of the delay on temperature, and the variance caused by the manufacturing processes.
For a Low-Pass with bandwidth BW you will get a delay of ~0.35/BW . I would start from this relatioship. For example, take a look into https://www.thorlabs.com/images/TabImages/Rise_Time_3dB_Bandwidth_Relationship_Lab_Fact.pdf .
Regards,
It all depends on the bandwidth of the signal of interest which is the very first thing to determine/assess. Then what Ionel Marius Vladan mentioned applies. The other thing is the specific application. For example, if you build say frequency analyser and intend to measure a phase shift between input and output signals then the overall delay of the circuitry will influence your phase shift accuracy.
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