High-end APIs of python, Tensorflow and Keras dramatically reduce the time and effort put into experimenting and deploying DL/ML models for various tasks. but I can't seem to find a High- level framework that quickly implements these algorithms on FPGAs.
What is the reason behind this? Is there any framework which helps me quickly experiment on FPGA?
As a design platform you can use Simulink/matalb. You can design the system in Simulink building blocks and the you can compile it into VHDL using the XILINIX SYSTEM GENERATOR.
As an example we designed the the acquisition and tracking phases of the GPS receivers on FPGA using such suite.
For details please follow the link: Article FPGA Implementation of Tracking Phase of the GPS Receiver Using XSG
and the link:
Article FPGA Implementation of Acquisition Phase of the GPS Receiver Using XSG
Best wishes
look-up this:
http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/AIML/NeuralNetworkCompiler
Maybe this goes into your direction.
As a design platform you can use Simulink/matalb. You can design the system in Simulink building blocks and the you can compile it into VHDL using the XILINIX SYSTEM GENERATOR.
As an example we designed the the acquisition and tracking phases of the GPS receivers on FPGA using such suite.
For details please follow the link: Article FPGA Implementation of Tracking Phase of the GPS Receiver Using XSG
and the link:
Article FPGA Implementation of Acquisition Phase of the GPS Receiver Using XSG
Best wishes
Abdelhalim abdelnaby Zekry Thank you for your answer. I am fimiliar with the Xilinx system generator. However, what I am specifically looking for is a way to quickly test different fault diagnosis algorithms established in our lab in real time. I would like to be able to see their response time. I was just wondering that a high-end API built on top of HDLs would have huge amount of applications so why I couldn't find one. Edward M.D. Fisher thank you for your input to this thread. your answer is what I was looking for.
Dear Sanaullah Mehran Ujjan , you have to remember that VHDL is a language that allows the specification of digital hardware designs, in which basically, you perform multiple tasks in parallel, so you use different constructs for concurrent processing of tasks (ex. additions, multiplications, hardware algorithms, etc). VHDL is not for sequential processing, so there is no direct translation from serial C/Python codes. HLS and OpenCL attempt to identify parts of C code which can be parallelized, and you use pragma like sentences at the beginning and end of C code sections for parallelization. This is one of the main reasons why you would not be able to find a framework to translate serial codes (such as C/Python) to hardware specification.
Regarding the problem (fault diagnosis algorithms) you try to solve, first, you must identify if the algorithms are serial, if there is no dependency between iterations, and if there are no dependencies, you can "parallelize" the algorithms, using a FSM to construct a hardware algorithm, resembling the serial version of the algorithm.
Regards,
Aurelio Morales-Villanueva Thank you for your input. thats really insightfull
Altium nanoboards are available where FPGA programming can be done using C. Xilinx has introduced PYNQ, an open-source using Python and libraries to use Xilinx platforms easily. http://www.pynq.io/
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