I am working on a multi-level DC link inverter. I have verified the simulation part in MATLAB/Simulink for R and RL load. when it comes to hardware for R load results are satisfactory, for RL load there is a small voltage dip or surge when the load current crosses zero instant.
Thank you for giving your response.
If it is a switching problem, why it has to come for RL load only? why not for R load. I am not getting this problem in the case of R load.
It is probably due to the fact that inductances try to keep the current "stable" independently of the voltage, so if a "freewheeling" condition occurs in power electronics due to a switching transition, the inductance will inject it's stored energy in the system and will modify the voltage creating a "dip", this will not happen with a resistor.
Besides the absence of a time scale and tags with a schematic, the fundamentals are out of phase and there are parasitic coupling capacitance spikes such as from a transformer and diode pF and probably along with parasitic ESL in the current path not accounted for in your model.
The in circuit inductance could produced little voltage at zero crossing as V=do/dt =(do/di)(di/dt)=L(di/dt), the current(flux) direction changes at zero crossing, could be improved by providing parallel cepecitor (C) .......
Thank you, for responding and giving
clarification on my problem. Why these reflections are not shown in Matlab/simulnik. (In simulink I have used rlc branch as a RL load)
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