I am implementing raddix-4 DIF generic algorithm (N = 64,256,1024,4096,16384) on xilinx virtex-6 fpga. I have got two schemes for the twiddle factor generation for that.
1) generate sin and cos by cordic and store it in memory and call it in the process to multiply with the addition of inputs. In this I can do parallel tasking to increase speed but multiplication increases vector length drastically.
2) use cordic rotation for complex multiplication. This will not increase vector length but will reduce my speed. Xilinx CORDIC ip core takes phase input in 2QN formate but my maximum multiplication (2*π*k*n/N) answer lies in 3QN formate (around -4.71). So how can I solve this problem?
If I understand correctly, you have the problem, that you give the DSP48s a 18bit and a 18bit vector and get out a 36bit answer?!
I am doing the same on our system and I would recommend looking at the input and output. Our sine and cosine for example are always < 1. In consequence even though the tools will give you a 36bit output the top bits will always be 0, so you can just chop them off(be careful not to chop sign bits).
The bottom bits are more a question of what the accuracy of your inputs is. Generally if the inputs are only accurate to 18bits, then you do not need to keep 36bit, but can chop off at least down to 20bits without increasing the error on the output significantly (all your are essentially doing is chopping off the already erroneous bits and thus only changing the nature of the error).
Hope this helps.
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