You haven't say nothing about signal bandwidth, about number of antennas etc. It is difficult to answer your question. Please, give more details.

Generally, FPGA is preferable for high-speed designs

Hallo, your system parameters are missing.

However, for small BW, you can use USRP modules (http://www.ettus.com/). If your antenna array will have more than two antennas, you need to buy an external source to provide frequency clock and PPS. There are many options also in the market using FPGA.

For large BW, you can use the Wideband MIMO PXI Vector Signal Analyzer (http://www.home.agilent.com/en/pc-2111539/wideband-mimo-pxi-vector-signal-analyzer), which is very high expensive.

DSP u processors like TMS320 Family.

We need to know more about your system requirements in order to put a specification on processing throughput and memory requirements.

In the absence of this knowledge, I will say that I have found the Analog Devices Blackfin series to be an excellent choice for many DSP projects. On top of that, there are many Open Software tools available for the Blackfin (uCLinux, real-time tools, etc.) that can speed system development at a modest cost compared to expensive toolchains needed for TMS series. If your DSP load is not so demanding, perhaps a PIC or Atmel processor would be in order.

Of course, the most demanding high-throughput DSP is always done using FPGA.

Thank you for replies. My requirements are as of time for an array of 30-50 elements with around 100 MHz bandwidth. Each and every time I need to collect the information of the input power at each element and then compare it with that of stored in a memory. Is this possible using the above suggested FPGAs or DSPs?

ok...if you want to process the full 100 Mhz bandwidth in real-time, you are probably looking at banks of FPGAs running at sample clocks of at least 200MHz (better still 400-600MHz to take advantage of noise benefits of oversampling) with enough logic cells to do whatever it is you want to do. This would be digital front-end processing ("front-end" in the traditional RF sense: sampling IF output of downconverter and performing data reduction, e.g. filtering, demod, etc. to feed to the back-end processor). Back-end processing (driving control lines of FPGA system and further data reduction and interacting with the user interface/PC) can be done on a traditional DSP processor.

Respected George Slade, can i have any related article which can pin pointedly give this information more elaboratively? Also if just want to restrict the design to a single dsp or FPGA (not banks of FPGAs), what is the bandwidth limitation?Thanks in advance

Dear Kavya, you are making the fatal mistake of not defining your requirements before defining the specification of your system. What exactly do you want to do? Real-time pattern steering? Interference mitigation? User identification? Radar target identification/tracking? Each of these tasks has different resource requirements. A random "dump" of articles or advice does not seem appropriate at this time. Please tell us more about what you want to do and perhaps we could help...

Sir my apologies for not being able to project my question properly as I am a starter in this field. Sir, actually I have completed designing an array antenna of 32 elements where adaptive correction of its coefficients can be done using adaptive mean squares algorithm. Now my intention is to develop a hardware module using DSPs or FPGAs for real time pattern steering and as well as to monitor any degraded performance of the antenna and correct it. Since you have mentioned about the banks of FPGAs to monitor complete bandwidth of 100MHz with a centre frequency of 12.5GHz, I wanted to go from the basic design of a single FPGA or DSP which supports my work. I hope now I am much clear. Please advice me considering me as a beginner

The front-end I/O of your array alone will be a prohibitive factor, if you truly want to sample all of the antennas and do beamforming in real time. A single DSP or FPGA board will have a limited number of A/D converter channels, a limited sampling rate, and a limited amount of memory to hold the samples. Even if you can get all of that data into a single processing element, your algorithm will need to be fast enough to go through it all. Even if you use banks of FPGAs you would typically decimate your data as soon as possible to allow you to do any kind of useful processing. That is a big part of the motivation for the question about what you mean to do with the data.

Respected Joseph thank you very much for the reply. Now I got some clarification on my doubt.

Besides a bandwidth to be sampled you also have to take in account functionality. You didn’t mention but I imagine that you pretend to do multiple beams? Other important feature is that your digital processing part has to provide calibration of the antenna. All these facts has significant impact on architecture of the digital platform.