Conducted EMI could be simulated with SPICE-like software. We tried to perform similar simulation at our university. Parasitic RCL should be added into the circuit to make simulation more realistic. But radiated EMI always requires  EM-simulator to estimate them.

Thank you, Vadim! If you have published something on this topic I will be happy to read. Is your method suitable for switched capacitor converters, where there is no inductor? I'm interested in exploring this case deeper. We can joint our efforts and as a result write a paper. 

The supervisor of my PhD thesis (Prof. L.Kechiev, Radioelectronics department, Moscow Institute of Electronics and Mathmathics) was one of the leading experts in field of EMC in Russia. And all work in field of EMC simulation is reflected in open archive of the "EMC Technologies"  journal that is published by MIEM. You can can find this archive here: http://emc-journal.ru/?q=node/4 (in Russian). I am specialized in field of ESD simulation, but I have studied different aspects of EMC (including EMI simulation) during my PhD thesis preparation. I haven't work with switched capacitors circuits previously, but I think we can join our efforts.

This journal Vadim, has only strengthened my suspicions. The sphere of EMI is so big that it is hard to sink a deep well :) Let's take some simple example that you familiar with and analyze it. Probably, after that we can add something and pass to EMI on-chip. Do you know the old book, Henry W. Ott, Noise reduction techniques in electronic systems? Is it still relevant?

Alexander, sorry for delay. Here is simple example that illustrates approach used at our department for EMI simulation. It is controlled SCR rectifier. The EMI level transferred into the power source is simulated. I attach its schematic. Elements L1L2C1C2R3R4 represent line Impedance stabilization network (LISN). The EMI signal is taken from the virtual LISN output.

To my understanding, the bottom figure shows the current through the SCR, and EMI is measured as a FFT of the voltage difference after high-pass filtering. Why this specific signal is considered as an interference for the input source?

> the bottom figure shows the current through the SCR

Yes, the bottom plot is SCR current, and the upper is EMI spectrum.

> Why this specific signal is considered as an interference for the input source

It is common method of the EMI level measurement. This spectrum is the input of the EMI receiver (selective microvoltmeter) that is connected to the output of the LISN. And real EMI receiver should show this spectrum.

What kind of EMI do you wish to simulate: EMI generated by an IC in power/signal lines, or susceptibility of an IC to external EMI? The second variant is also may be possible.

Thank you, Vadim. Yes, let us for the sake of simplicity, consider the pair of "transmitter" and "receiver". Of course, there is a "channel" with these or those properties, where interferences pass and interact. This PhD thesis can serve as a good starting point for modelling the on-chip EMI 

E. Backenius, "Reduction of Substrate Noise in Mixed-Signal Circuits," 2007

http://liu.diva-portal.org/smash/get/diva2:23520/FULLTEXT01.pdf

Alexander, thank you for this thesis. It contain very interesting materials. I need to learn it more deeply. I think switching noise simulation could be performed at the SPICE level. I will try to simulate it with Qucs-S.

Vadim, I'm also learning the principles described in that thesis and will be happy to elaborate this topic with you. It takes time, and right now I'm preparing to upcoming conference...

Alexander, I have first results with Qucs and Ngspice. I have emailed it to you.

Thank you, Vadim! The simulation you carried out is very interesting. I would like however, to clarify some details. The input pulses have the amplitude of 3.3V, while the power supply is 5V, why? The load capacitance of the inverter, 1pF, seems to be too low. Is there any reason for that? What effect the load resistance of 22k should describe? Is this some effect specific for 74HC series? By the way, does 74HC series presume equal on-resistances of nMOS and pMOS? If so, the width of pMOS (now 360um) should be greater at least 2.7 times than that of nMOS (now 140um). If we are talking about the standard CMOS ICs, why do not use 74LVC series? Its SPICE model can be found here http://www.nxp.com/products/discretes-and-logic/logic/lvc/hex-inverter:74LVC04A?tab=Design_Tools_Tab

For deep-submicron technologies there are also free predictive SPICE models available from http://ptm.asu.edu/ 

The general disadvantage of using SPICE models is apparently in that they force us to use external passive components. Could they reflect post-layout effects, I do not know. Probably, in this sense IBIS models are better.

As to advanced simulations, a good and demonstrative example would be ring oscillator. It is a particular case of the so-called Muller pipeline, shown here http://www.karlfant.net/flow-computation/coupled-oscillators

Alexander, here are my explanations on this simulation:

> The input pulses have the amplitude of 3.3V, while the power supply is 5V, why?

I have tested different combinations of input/power voltages. 5V/5V also works.

> The load capacitance of the inverter, 1pF, seems to be too low. Is there any reason for that?

No, there was no reasons for such RC values. It is an abstract load. Ngspice fails sometimes when circuit simulated without load. Higher C (10-12pF) gives lower EMI level (up to +20 dBuV max).  I have also tested it.

> By the way, does 74HC series presume equal on-resistances of nMOS and pMOS

Transistors models were taken from LTSpice 74HC library: http://ltwiki.org/files/LTspiceIV/lib/sub/74hc.lib It could be replaced by any transistor model. For example, MOSIS transistors could be used.

> If we are talking about the standard CMOS ICs, why do not use 74LVC series?

It is not a problem. 74LVC series also could be simulated. I have selected 74HC series, because I often use it in my projects.

> Could they reflect post-layout effects, I do not know.

IC layout LCR-parasitics are represented by lumped elements. Also transmission lines models could be used. There may be weak correlation of layout parasitics values and EMI level. I have an impression that EMI level is mostly determined by PCB layout. It's need to investigate this using parametric simulation.

> Probably, in this sense IBIS models are better.

SPICE model will give the better precision. EMI level mainly determined by output switches. And we don't need a full SPICE model. Input and output circuits may be in SPICE, and internal IC block may be a digital XSPICE device.

> As to advanced simulations, a good and demonstrative example would be ring oscillator. 

This information is very interesting. I also had thoughts to simulate an EMI induced by some CMOS oscillator. I will learn this link.

Well done, Vadim, let's keep going ahead. I think that main efforts and hopefully main results should relate to state of the art technology, namely bulk CMOS. Yes, for 28 nm and below there are HKMG, FinFET and so on, but as far as I know, they have many restrictions for layout. I suggest to start from revisiting the basics from the new book by Henry Ott    

http://www.emcs.org/acstrial/newsletters/spring10/BookReview.html

An advanced material regarding the substrate noise is given in

http://ieeexplore.ieee.org/document/4232941/

http://ieeexplore.ieee.org/document/5290343/