I am fabricating metal oxide TFT on SiO2(300nm)/Si(p++) substrate. In output characteristics I am observing minor linear modulation of Ids with change in Vgs but unable to get Ids saturation for as-deposited samples and linear modulation improves after air annealing. I also tried active layer of different thickness and vacuum annealed the samples still no saturation was found.
There was no gate current leakage in device.
Note:
Structure: inverted staggered; W/L= 2000/100 um
Reactive dc magnetron sputtering for active layer deposition; S&D= Ag (thermal deposition)
Characterization: Keithley 4200 SCS
Attached below are O/P and Transfer Characteristics of samples after Air annealing
What is the current density in the transistor? That also determines the saturation current. Maybe you simply are using currents that are too low.
General FET equation : Ids is proportional to Cox and mobility of electrons for an applied VDS . Check the values theoretically at least for saturation that is dependent of W/L , Vth
Another problem that I see is a relatively low gate control over the channel. It could be interesting to try multi-frequency Cg-Vg and get a qualitative idea of the Dit.
Also, there are very few details about the semiconductor; have you verified its properties? Is it continuous, uniform? Could series/contact resistance be an issue? Can you try TLM?
Thank You all for Response and sorry for late reply.
Dear Tony Maine,
Sir we tried biasing the device above 70V, but then device shorted and we started observing burn spots on S/D pads.
Dear Aparna Sathya Murthy,
Ma'am i didn't check that i ll see. Can you please forward some literature or research paper regarding that.
Dear Lior Kornblum,
Sir we tried C-V measurement for Vg= -30 to 30V, we didn't observe any accumulation to depletion transition in curves just a small linear increase in capacitance.
The film is continuous and uniform. We tried TLM and getting negative y-intercept. i-e nevative value of contact resistance
Seems to be a book , exactly your scale (300nm)
Polycrystalline Semiconductors: Grain Boundaries and Interfaces by Hans J. Möller, Horst P. Strunk, Jürgen H. Werner - 2012 - Technology & Engineering
Google it - Same equations looks like !!
Pritam,
What is the TLM sheet resistance that you extracted?
If you don't see depletion, do you expect to be able to switch off the device?
Dear Aparna,
Thank you ma'am i ll look into it.
Dear Lior,
Sir did you mean TLM contact resistance which i extracted?
sir we are working on enhancement mode TFT.
I meant the sheet resistance (Rs) taken from the slope of the TLM curve.
Dear Lior,
Sheet Resistance taken from slope of TLM curve was found to be in the range of tens of Mega-Ohms.
Dear Thomas,
Thank You For response, Semiconductor was just deposited by reactive sputtering and no doping was done.
Pritam,
Did you use appropriate gate bias: Vds=Vgs-Vt, it seems channel is not pinching off. What you currently have is Vds=Vgs-Vt. I am not sure what gate bias you used? Did you satisfy these conditions so that it can be make sure that channel is pinched off. The voltage drop between pinch off point and drain needs to be constant and I think the problem having there.
Dear Min Khanal,
Thank Your for your response, Gate bias used were from 0V to -70V with a step of 10V . Biasing any input terminals above 70V resulted in burning of electrode pads and device would fail (high gate leakage starts).
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