I want to work on Power Delivery Network of an electronic device (microprocessor/silicon chip). Please share your valuable suggestion and guidance to work on this field.
Thanks in advance for helping me.
By Power Delivery,apart from Electical Power Delivery,We also mean Power Delivery to Electronic Devices, like from PCBs,Power Delivery for Multi Core Servers etc..
1. The goal of a power delivery network is to provide clean power and reference voltage
to the active devices on the die. Similar to an ASIC, field programmable gate array
(FPGA) devices need clean power to meet their maximum operating frequency (f
MAX)specifications. A simple representation of a system power delivery network.
http://www.altera.com/literature/an/an574.pdf
Power Delivery Network (PDN) Design Methodology. This application note provides an overview of the various components that make up a power delivery network.
2. http://cseweb.ucsd.edu/classes/wi06/cse291-b/slide/let2/power.pdf
New Power Delivery Architecture and Thermal Considerations for Multi Considerations for Multi Core Servers..
Optimization of Package Power Delivery and Power Removal Solutions to meet Platform level Challenges
P.S,
The following References may give an idea of Resarch Areas in Power Delivery Networks.
1. Challenges and Recent Research in On -Chip Power Delivery
By Eby G. Friedman
http://acrc.ee.technion.ac.il/uploads/file/18_7_10/Friedman_Challenges_Power_Delivery_Technion_July_10.pdf
2. PDN in 3d Stacked Memory Devices
By Manjunath Shevgoor et al
http://research.ihost.com/weed2013/papers/pdn.pdf
3. Simulation and Optimization of On-Chip Power Delivery Networks and Clock Networks
By Dr. Sheldon Tan and his team
http://www.ee.ucr.edu/~stan/project/pg_ana/pg_proj.htm
4. Understanding Voltage variations in Chip Multiprocessors using a Distributed Power Delivery Network
By Meeta S. Gupta et al.
http://www.eecs.harvard.edu/~meeta/my_papers/date07_cmp.pdf
5. High Performance Power Distribution Networks with On-Chip Decoupling Capacitors For Nano Scale Integrated Circuits.
Ph.D. Thesis of Mikhail Popovich.
http://www.ece.rochester.edu/users/friedman/papers/Mikhail_Popovich_PhD.pdf
1. Challenges and Recent Research in On -Chip Power Delivery
By Eby G. Friedman
http://acrc.ee.technion.ac.il/uploads/file/18_7_10/Friedman_Challenges_Power_Delivery_Technion_July_10.pdf
2. PDN in 3d Stacked Memory Devices
By Manjunath Shevgoor et al
http://research.ihost.com/weed2013/papers/pdn.pdf
3. Simulation and Optimization of On-Chip Power Delivery Networks and Clock Networks
By Dr. Sheldon Tan and his team
http://www.ee.ucr.edu/~stan/project/pg_ana/pg_proj.htm
4. Understanding Voltage variations in Chip Multiprocessors using a Distributed Power Delivery Network
By Meeta S. Gupta et al.
http://www.eecs.harvard.edu/~meeta/my_papers/date07_cmp.pdf
5. High Performance Power Distribution Networks with On-Chip Decoupling Capacitors For Nano Scale Integrated Circuits.
Ph.D. Thesis of Mikhail Popovich.
http://www.ece.rochester.edu/users/friedman/papers/Mikhail_Popovich_PhD.pdf
1. Challenges and Recent Research in On -Chip Power Delivery
By Eby G. Friedman
http://acrc.ee.technion.ac.il/uploads/file/18_7_10/Friedman_Challenges_Power_Delivery_Technion_July_10.pdf
2. PDN in 3d Stacked Memory Devices
By Manjunath Shevgoor et al
http://research.ihost.com/weed2013/papers/pdn.pdf
3. Simulation and Optimization of On-Chip Power Delivery Networks and Clock Networks
By Dr. Sheldon Tan and his team
http://www.ee.ucr.edu/~stan/project/pg_ana/pg_proj.htm
4. Understanding Voltage variations in Chip Multiprocessors using a Distributed Power Delivery Network
By Meeta S. Gupta et al.
http://www.eecs.harvard.edu/~meeta/my_papers/date07_cmp.pdf
5. High Performance Power Distribution Networks with On-Chip Decoupling Capacitors For Nano Scale Integrated Circuits.
Ph.D. Thesis of Mikhail Popovich.
http://www.ece.rochester.edu/users/friedman/papers/Mikhail_Popovich_PhD.pdf
P.S.
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