I am a researcher in Silicon Photonics (also known as CMOS photonics). Sometimes I was in trouble because I do not have real experience of CMOS-compatible process, and I will doubt if the designed process for photonics material or device is really CMOS-compatible. For example, co-sputtering technique, high temperature thermal annealing, are CMOS-compatible? What is the criteria to judge?
Any discussion is welcome. Thank you very much!
Dear Dr. Armando Loni,
Thank you very much for the answer. I appreciate my lucky to receive discussion with expert!
I think I need some book or paper to know better about the traditional CMOS process, then I can judge whether or not the add-on process will affect the pre-processed regions. Do you have something to recommend?
And I have 2 detailed questions:
1. What is the safe temperature range for thermal annealing?
2. Any film deposition process, such as PECVD, sputtering, etc., may introduce Metal contamination, are not CMOS-compatible, is it?
Thanks a lot!
With best regards,
Min
Min Xie,
With regards to your latest set of questions, I'd like to add some feedback, as I understand it .....
Metal deposition steps may happen more than once in CMOS-compatible processes. Let me rephrase for the purists -- if you look at a CMOS process cross-section diagram, you can see 2-3 metals deposited with different techniques. There are also other materials which have metals e.g., TiN. You cannot rule out metal deposition all together as being CMOS in-compatible. It is what you do before or after that decides the outcome. For example, if you have Aluminum somewhere and you anneal at 700C, your aluminum will begin to become soft and migrate into other layers. If you have Copper somewhere, it can cause mid-band doping (i.e., previously insulating areas may not be perfectly insulating anymore) due to Copper migration due to heat. If you have a washing process that introduces sodium (Na+), that brings into play many more issues.
I feel uneasy suggesting any annealing temperature as everything must be judged on a case to case basis and you have to read at each step. During my studies, I got the sense that for most materials (except polymers), SiO2. It depends.
I would like to add a comment here from Prof. Martijn Heck, and many thanks to his discussion:
"CMOS compatibility is indeed one of the most abused terms in photonics. Bottomline is that photonics as we normally know it and state-of-the-art CMOS cannot be made on the same chip. This has several reasons, but most importantly, as Gunther points out, the dimensions are at least an order of magnitude off, in basically all directions. And the gap is growing, with the ever decreasing gate lengths. Photonics is stuck, due to the wavelength, but plasmonics might bridge the gap.
That being said, there are efforts to bring photonics and CMOS to the same chip, in a fully compatible process. Luxtera uses/used 'large' CMOS (forgot the node size) and combined it with silicon photonics. That seems to work well, although in terms of footprint mismatch and yield, I do not know whether this is a good approach. But I am not making the business out of it, they do. Also IBM uses this approach.
MIT (Rajeev Ram group) has some nice deposited silicon photonics, added in the back-end process. This was completely made in a CMOS fab, in a state-of-the-art process. Again, I do not know the node number by heart.
You see a lot of work on silicon nitride, including work by me an co-workers. This is definitely not CMOS-compatible, since you need very high (over 1000 deg) anneal temperatures. It is, however CMOS fab compatible, and we have shown that we can make ultra-low loss waveguides based on silicon nitride in CMOS fabs. We called this "CMOS fabrication infrastructure compatibility". Do not underestimate the value of that, though."
CMOS compatiblite photonic integration is an effort to fabricate photonics components and CMOS circuits in a single Si die. You may be interested in one of the example found in literature, CMOS compatible Photonic device works in terahertz regime.
Hope this paper helps you. "Hübers, Heinz-Wilhelm. "Terahertz technology: Towards THz integrated photonics." Nature photonics 4.8 (2010): 503-504."
When you speak about CMOS compatibility, you need to consider the following things:
1. Keep the temperature low so that dopant re-distribution will not happen
2. Make sure that the metals are not getting oxidized or transformed into other form
3. Use materials that will not create any defects in the critical oxide layers such as gate oxide of MOS
This is not an exhaustive list. There could be more points that may be added to this.
Jose
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