I am guessing you build a series of OTFTs on a large piece of Si wafer and you are depositing your organic semiconductor over the entire substrate area? If so, there are several things you can do:

- Prior to measurement, take a tooth pick or something similar and make a scratch around each transistor on your substrate, so that you remove the organic semiconductor in the scratched region, but do not damage the substrate. This should have a similar effect to structuring your organic semiconductor during deposition (which of course you can also do if you have the tools available).

- Take a careful look at the quality of your gate dielectric. I am guessing that you are using thermally grown SiO2 of a standard thickness, something like 300nm? Depending on where you get this from, the quality of the oxide may be quite poor, so if you have the chance, try to get hold of wafers which are covered in ALD-grown aluminum oxide. It's thinner, usually better quality (i.e. less pinholes) and you don't have to worry about passivation so much.

- See if you can decrease the size of your S/D contacts without affecting transistor performance. You might have excess electrode area which is not really contributing to channel formation, only to the gate leakage

Dear Fiheon

Would you please give the detailed structure of your OFET.

The leakage current can be across the gate insulator as an excessive gate current. This is normally due to too thin oxide permitting tunneling across the gate insulator. It can be reduced by treating the thin oxide by Using Molecular Dipole Mono layers  according to the paper given in the attached link:https://www.researchgate.net/.../248704424_Reducing_Leakage_Currents_in_n-Channel...

If the leakage between the drain and source is too high , then one has to reduce the conductivity of the intrinsic material in the channel by elaborating the deposition process. In this case the conductivity of the organic materials will be sufficiently small  and the leakage current will be reduces.

Best wishes

If you depositing organic semiconductors over the entire Si/SiO2 substrates, as Dr. Hauke suggested, then the high gate current (Ig) is not really leakage current through SiO2 layer (our conventional perception of leakage current in TFTs). Dr. Hauke's suggestion of using a toothpick to isolate your individual OFET from the entire organic semiconductor film is similar to what we do to reduce Ig in our measurements. We use the measurement probe instead (because our devices are very small and can only be seen clearly under the microscope).

In practical OFETs, they are patterned (by lithography for example) to isolate each individual OFET from the whole substrate.