I guess , low power design books will elaborate as to how we can optimize the power that is being consumed and hence dissipated. You can begin with architecture level for design of a system and start looking at the power consumed when they are doing a job. The major blocks such as register(s), counters, ALUs etc , for instance gating them if clock is fed but is not needed Eg: ALUs . Then you can refine the design and optimize it , say by inspection you find some other signal lines are routed ! (assuming non-standardized algorithm is used for these blocks...). You can then go to gate level and check for switching frequency , capacitance (stray) and static currents  so that you can increase or  decrease (in #) and characterize for optimization (Or you can go reverse , ie start with transistors, gates, data-path elements and then processor/memory etc).

If you use HDL , you can start at the RTL design and optimize it to the transistor level and use it as a fundamental cell.

I referred to : Practical Low power VLSI design by G K Yeap

Dynamic power management design  technique and CAD tools  by G de Micheli et al

This is the first answer,  and therefore very simple-minded.  Doubtless the discussion will become more sophisticated and interesting as more knowlegable people enter.

When integrated circuits are operating currents are flowing in each device:  the devices themselves are semiconductors and have a (low, but non zero) resistance in the ON condition,  and all the charge has to be transported to the device from the supply rails through the metallic interconnects,  which also have a low (but non-zero) resistance.  V=IR,  so given the current and the resistivity,  the power loss is inescapable.  Also,  each device in the OFF condition is a reverse-biassed diode which also has a leakage current.  The relatively high power consumption of modern instruments (laptops etc) is because they have large numbers of transistors, and although each has a rather small leakage.

So much is obvious,  other contributors can put numbers on this,  I am sure.  There are lots of tricks to reducing power consumption.  The first and most obvious is the invention a generation ago of CMOS (as opposed to nMOS or pMOS),  which balanced npn and pnp transistors so that active power was used only during switching.  Then it is a matter of getting all the material details right, and improving material properties.  This gets very complicated very quickly!

Thank you very much for the answers,

but if we can dive a bit more deep get a bit more specific details on the values and various ways in which processors dissipate the power consumed during its different states like peak working, medium working, idle stand by etc and how much heat is practically generated would be very much useful and appreciated.

Thanks once again and expecting more answers.

First, I found that no power is generated but only dissipated in a processor when in use, and the power is, of course, in a form of heat. You divide it correct (as in the following answers too) to three parts: due to leakage, direct heating (due to the limited conductance of the elements and wires) and to dinamic power, I mean the power dissipated in the process of switcung from "zero" to "one" positions of evety element. This power is actually the power "in a processor when in use" and it is of the main quantity. I hope you realize that the processor is heated mainly when it is used in a great massive of operations.

In my opinion, this power cannot be optimised but only can be minimised via increasing the speed of operation. Some optimization can be realized by optimising the softwear, but I mean this is a question from an another  field.

In general power dissipation occurs due to following reasons:

Dynamic power consumption: Due to logic transitions causing logic gates to charge/discharge load capacitance.

Short-circuit current: In a CMOS logic P-branch and N-branch are momentarily shorted as logic gate changes state resulting in short circuit power dissipation.

Leakage current: This is the power dissipation that occurs when the system is in standby mode or not powered. There are many sources of leakage current in MOSFET. Diode leakages around transistors and n-wells, Subthreshold Leakage, Gate Leakage, Tunnel Currents etc. Increasing 20 times for each new fabrication technology. Went from insignificant to a dominating factor.

Hope these information are useful.

Book:

Power-efficient System Design