Dear Nandan Kumar Jha,

"50% duty cycle" concept is ('high' time = 'low' time). And this is in general in order to obtain a count sequence where each and every step pauses for the same amount of time.

However, duty cycle can be modified according to the requirement. And the procedure and the basic concept is that "the basic square wave generator signal can be modified to obtain an adjustable duty cycle pulse generator, by providing a separate charge and discharge path for capacitor hence the difference in rise and fall".

And in many situations we use duty cycle less than 50%.

As setup time is dependent on clock frequency but not on clock duty cycle while hold time is independent of clock frequency. So my doubt is " Is it possible to make a system more immune to clock skew by changing the duty cycle of clock" ?

Dear Nandan Kumar Jha,

Make an exp[eriment. Design a 4-bit up counter with JK flip-flops. The FF (LSB) is connected with function generator and this FF is positive edge triggered. The others FFs are hooked with negative edge triggered. These FFs are triggered by their depressor's FF's state.

generally digital circuits dissipate power when they transit from one state to the other state. the transistors dissipate more power in active region than the saturated regions. thus I think, low duty cycle will not have major impact on power dissipation.

... and this is typical for CMOS family...

how to adjust the duty cycle. i have generated a square wave and i want to reduce the on time of square wave..i have used pll to get square wave of 4mhz from source of 50 mhz.. now i want to reduce on time how i can do that any idea? also if u have any other ways to do so with other circuit design then all are welcome. RSVP