I'm looking for an analytical model to detect the effect of the memory system on the performance of multi-core processors? Like the number of levels in the memory hierarchy and the size of each level. Taking into account the application type.
please read this paper.
https://vtechworks.lib.vt.edu/bitstream/handle/10919/51255/Su_C_D_2015.pdf?...1
http://www.cse.wustl.edu/~jain/cse567-11/ftp/multcore.pdf
http://www.cse.wustl.edu/~jain/cse567-13/ftp/multicore.pdf
http://www.iaeng.org/IJCS/issues_v39/issue_3/IJCS_39_3_11.pdf
http://www.ideal.ece.ufl.edu/publications/files/286-James-go-press.pdf
https://www.cs.sfu.ca/~jpei/publications/sc12.pdf
https://vtechworks.lib.vt.edu/bitstream/handle/10919/51255/Su_C_D_2015.pdf?sequence=1
http://www.xcg.cs.pitt.edu/papers/oh-mascots11.pdf
You can refer these papers.
Good luck.
Well Ahmed ,
If you haven't looked at it the L1,L2,L3 ... (hierarchy )would be a starting point. Again cache since it is faster as against RAM (mapping is the key).
Replacement algorithms (LRU for data cache) are pretty standardized , for eg: direct mapping or Associative.Alternates I am sure are variants of this (LRU).
This is a good read: Memory Hierarchy in Cache- Based Systems for High performance computing (the then Sun micro system ) .
With multi-core hardware, memory accessibility should be more exclusive ...
Thank you all for your help. I'm working on a mathematical model using Markov chains with one of my students. Once we finish I will share the results with you.
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